A 50 ms/s First-Order Mismatch Error Shaping and Third-Order Noise-Shaping SAR ADC for IOT Applications

Abstract

This article presents a first order Mismatch Error Shaping (MES) and third-order Noise Shaping (NS) Successive Approximation Register (SAR) analog to digital converter (ADC). We choose fully dynamic hardware reusing (HR) error feedback, cascade of integrators with feed forward (EF-CIFF) structure to reduce the power consumption, and to increase the sampling speed. In addition, to enhance the resolution, a MES scheme with two-level digital prediction is implemented to remove the distortion caused by the capacitive digital to analog converter (CDAC) mismatch. The SPICE level simulations of the proposed ADC implemented using a 28-nm CMOS process show 85 dB signal-to-noise-distortion ratio (SNDR) with 1.56 MHz bandwidth (oversampling ratio (OSR) = 16).