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Cited 4 time in webofscience Cited 5 time in scopus
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Fast compact true random number generator based on multiple sampling

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dc.contributor.authorChoi, Piljoo-
dc.contributor.authorLee, Mun-kyu-
dc.contributor.authorKim, Dongkyue-
dc.date.accessioned2021-08-02T14:55:31Z-
dc.date.available2021-08-02T14:55:31Z-
dc.date.issued2017-06-
dc.identifier.issn0013-5194-
dc.identifier.issn1350-911X-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/19684-
dc.description.abstractA new ring-oscillator-based true random number generator (RNG) based on multiple sampling is proposed. The proposed generator uses the outputs of all gates in a ring oscillator, as positive-and negative-edge clock signals. The generator in two field-programmable gate array families is implemented, and it is verified that the generated bit sequences pass the RNG tests of the National Institute of Standards and Technology. The experimental results show that the proposed generator is faster and more compact than the existing ring-oscillator-based true RNGs.-
dc.format.extent2-
dc.language영어-
dc.language.isoENG-
dc.publisherInstitute of Electrical Engineers-
dc.titleFast compact true random number generator based on multiple sampling-
dc.typeArticle-
dc.publisher.location영국-
dc.identifier.doi10.1049/el.2017.1202-
dc.identifier.scopusid2-s2.0-85021300703-
dc.identifier.wosid000404115200013-
dc.identifier.bibliographicCitationElectronics Letters, v.53, no.13, pp 841 - 842-
dc.citation.titleElectronics Letters-
dc.citation.volume53-
dc.citation.number13-
dc.citation.startPage841-
dc.citation.endPage842-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClasssci-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordAuthorcontent-addressable storage-
dc.subject.keywordAuthorrandom-access storage-
dc.subject.keywordAuthorCMOS digital integrated circuits-
dc.subject.keywordAuthor3T-2R nvTCAM-
dc.subject.keywordAuthornonvolatile ternary content-addressable-memory-
dc.subject.keywordAuthorvoltage limiter-
dc.subject.keywordAuthorself-controlled bias circuit-
dc.subject.keywordAuthormatch line development-
dc.subject.keywordAuthorsensing margin-
dc.subject.keywordAuthorresistance ratio-
dc.subject.keywordAuthorsensing delay-
dc.subject.keywordAuthorCMOS process-
dc.subject.keywordAuthorsize 65 nm-
dc.identifier.urlhttps://ietresearch.onlinelibrary.wiley.com/doi/10.1049/el.2017.1202-
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