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Accelerating CNN Training With Concurrent Execution of GPU and Processing-in-Memoryopen access

Authors
Choi, JungwooLee, Hyuk-JaeSohn, KyominYu, Hak-SooRhee, Chae Eun
Issue Date
Oct-2024
Publisher
Institute of Electrical and Electronics Engineers Inc.
Keywords
Training; Graphics processing units; Convolutional neural networks; Pipelines; Electric breakdown; Bandwidth; Batch normalization; Switches; Scheduling algorithms; Random access memory; Processing-in-memory; convolutional neural networks; neural network training; GPU
Citation
IEEE Access, v.12, pp 160190 - 160204
Pages
15
Indexed
SCIE
SCOPUS
Journal Title
IEEE Access
Volume
12
Start Page
160190
End Page
160204
URI
https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/198112
DOI
10.1109/ACCESS.2024.3488004
ISSN
2169-3536
2169-3536
Abstract
Training of convolutional neural networks (CNN) consumes a lot of time and resources. While most previous works have focused on accelerating the convolutional (CONV) layer, the proportion of non-convolutional (non-CONV) layers, such as batch normalization, is gradually increasing during training. Non-CONV layers have low cache reuse and arithmetic intensity, thereby performance is limited by memory bandwidth. Processing-in-memory (PIM) can utilize wide memory bandwidth, making it suitable for acceleration of non-CONV layers. Therefore, it makes sense to perform the computationally complex CONV layer on the host and handle the memory bottleneck challenges of the non-CONV layer on the PIM. Further improved performance can be expected if they run simultaneously. However, memory access conflicts between the host and PIM are the biggest factors hindering performance improvement. Prior studies proposed bank partitioning to alleviate memory conflicts, but it is not effective because CNN training involves significant data sharing between CONV and non-CONV layers. In this paper, we propose a memory scheduling and CNN training flow for the pipelined execution of CONV layers on the host and non-CONV layers on PIM. First, instead of applying bank partitioning, the host and PIM exclusively access memory for a certain period to avoid the movement of shared data between host memory and PIM memory. The conditions for switching the memory access authority between the host and PIM are set per layer, taking into account memory access characteristics and the number of queued memory requests. Second, in the training flow, CONV and non-CONV layers are pipelined in units of output feature map channels. Specifically, for the backward pass, the non-CONV tasks of the feature map gradient calculation phase and the weight gradient update phase are rearranged so that they can be easily performed within CONV layers. Experimental results show that the proposed pipelined execution achieves an average speedup of 18.1% at the network level compared to the serial operation of the host and PIM.
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