Memory data reorganization for performance improvement of HEVC DCT

Abstract

DCT is the main performance bottleneck of the HEVC because it has a lot of repeated operations. Performance of the DCT can be improved by executing these repeated operations in parallel. However, memory operations to access the required data limit performance improvements of the parallelization. In this paper, we parallelize the DCT by using the ASIP developed in our previous work and propose an efficient memory data reorganization scheme to achieve further performance improvements of DCT parallelization.