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Garbage Collection for Low Performance Variation in NAND Flash Storage Systems

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dc.contributor.authorJung, Sanghyuk-
dc.contributor.authorSong, Yong Ho-
dc.date.accessioned2024-12-20T06:24:07Z-
dc.date.available2024-12-20T06:24:07Z-
dc.date.issued2015-01-
dc.identifier.issn0278-0070-
dc.identifier.issn1937-4151-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/202648-
dc.description.abstractIn many NAND flash-memory storage systems, invalidated pages can occupy the storage space until being erased. In order to preserve sustained write performance and effective storage capacity, the flash translation layer (FTL) must recycle these pages through garbage collection (GC) operations. Many previous studies have investigated GC techniques, most of which have focused on the effective selection of victim blocks to reduce the operational overhead. However, methods to reduce the cost overhead of the victim selection process, as well as to improve the responsiveness of storage systems during GC, have not yet been explored. In this paper, therefore, we propose a novel GC mechanism, called link-based GC (LINK-GC), which provides fast victim selection and preemptive operation with small additional space overhead to existing page-mapped FTLs. In our experiments, when compared with a GC scheme based on an on-demand victim search, the proposed mechanism increases the average input-output operations per second (IOPS) by up to 15.8% and decreases the standard deviation of IOPS by up to 6.16 times. Additionally, the LINK-GC shows better performance than the existing preemptive GC techniques in terms of responsiveness to host requests.-
dc.format.extent13-
dc.language영어-
dc.language.isoENG-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.titleGarbage Collection for Low Performance Variation in NAND Flash Storage Systems-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/TCAD.2014.2369501-
dc.identifier.scopusid2-s2.0-84919800762-
dc.identifier.wosid000348228400003-
dc.identifier.bibliographicCitationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.34, no.1, pp 16 - 28-
dc.citation.titleIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems-
dc.citation.volume34-
dc.citation.number1-
dc.citation.startPage16-
dc.citation.endPage28-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClasssci-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryComputer Science, Interdisciplinary Applications-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusMEMORY STORAGE-
dc.subject.keywordPlusTRANSLATION LAYER-
dc.subject.keywordPlusFILE SYSTEM-
dc.subject.keywordPlusARCHITECTURE-
dc.subject.keywordPlusENHANCEMENT-
dc.subject.keywordPlusDURABILITY-
dc.subject.keywordPlusDESIGN-
dc.subject.keywordAuthorData storage systems-
dc.subject.keywordAuthorembedded software-
dc.subject.keywordAuthorflash memories-
dc.subject.keywordAuthormemory management-
dc.subject.keywordAuthorscheduling algorithms-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/6954423-
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