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Design of an application specific instruction set processor for a universal bitstream codec
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Choi, Seung-Hyun | - |
| dc.contributor.author | Roh, Tae-Moon | - |
| dc.contributor.author | Song, Yong Ho | - |
| dc.contributor.author | Lee, Seong-Won | - |
| dc.date.accessioned | 2024-12-20T06:24:08Z | - |
| dc.date.available | 2024-12-20T06:24:08Z | - |
| dc.date.issued | 2014-11 | - |
| dc.identifier.issn | 1349-2543 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/202662 | - |
| dc.description.abstract | Recent increases in the type and amount of multimedia data has required a versatile device enough to play various data. Especially a variety of lossless compression algorithms often causes large amount of redundant computations. In this paper, an application-specific instruction processor tailored to effectively process such coding algorithms is proposed. The functionality and performance of the processor has been verified by using it to run the H.264/AVC baseline profile encoder. The experimental results show that the proposed processor can save about 96% and 36% of the execution cycles of ARM Cortex-A9 and Intel i7 processors, respectively. | - |
| dc.format.extent | 12 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | The Institute of Electronics, Information and Communication Engineers (IEICE) | - |
| dc.title | Design of an application specific instruction set processor for a universal bitstream codec | - |
| dc.type | Article | - |
| dc.publisher.location | 일본 | - |
| dc.identifier.doi | 10.1587/elex.11.20141047 | - |
| dc.identifier.scopusid | 2-s2.0-84919800447 | - |
| dc.identifier.wosid | 000348586800008 | - |
| dc.identifier.bibliographicCitation | IEICE Electronics Express, v.11, no.24, pp 1 - 12 | - |
| dc.citation.title | IEICE Electronics Express | - |
| dc.citation.volume | 11 | - |
| dc.citation.number | 24 | - |
| dc.citation.startPage | 1 | - |
| dc.citation.endPage | 12 | - |
| dc.type.docType | Article | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.subject.keywordPlus | H.264/AVC | - |
| dc.subject.keywordAuthor | ASIP | - |
| dc.subject.keywordAuthor | entropy coding | - |
| dc.subject.keywordAuthor | RLC | - |
| dc.subject.keywordAuthor | bitstream | - |
| dc.subject.keywordAuthor | H.264 | - |
| dc.identifier.url | https://www.jstage.jst.go.jp/article/elex/11/24/11_11.20141047/_article | - |
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