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Scalable approach for flash storage controller design
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Huh, Taeyeong | - |
| dc.contributor.author | Lee, Seolhee. | - |
| dc.contributor.author | Song, Yong Ho | - |
| dc.date.accessioned | 2024-12-20T06:24:11Z | - |
| dc.date.available | 2024-12-20T06:24:11Z | - |
| dc.date.issued | 2013-11 | - |
| dc.identifier.issn | 0000-0000 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/202704 | - |
| dc.description.abstract | Recently the PCIe interface technology is being widely adopted to bridge a host system and a storage device. The bandwidth scalability provided by this technology allows to satisfy various performance requirements on storage systems. However, a storage system tends to be administrated by a single controller whose technical specification is determined at design time, and therefore we need to design a new controller if the storage system needs to be expanded in performance and capacity. In this paper, we present a scalable channel slice approach for designing a flash storage controller. In this approach, a storage system is composed of channel slice modules each of which has a channel slice controller and flash memory devices. The proposed channel slice controller is designed by using the Verilog hardware description language, and its functionality and performance have been verified using simulation techniques. | - |
| dc.format.extent | 3 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | IEEE Computer Society | - |
| dc.title | Scalable approach for flash storage controller design | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.doi | 10.1109/ISOCC.2013.6863981 | - |
| dc.identifier.scopusid | 2-s2.0-84906911137 | - |
| dc.identifier.bibliographicCitation | ISOCC 2013 - 2013 International SoC Design Conference, pp 43 - 45 | - |
| dc.citation.title | ISOCC 2013 - 2013 International SoC Design Conference | - |
| dc.citation.startPage | 43 | - |
| dc.citation.endPage | 45 | - |
| dc.type.docType | Conference Paper | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.subject.keywordPlus | Computer hardware description languages | - |
| dc.subject.keywordPlus | Flash memory | - |
| dc.subject.keywordPlus | Scalability | - |
| dc.subject.keywordPlus | Virtual storage | - |
| dc.subject.keywordPlus | Bandwidth scalability | - |
| dc.subject.keywordPlus | Interface technology | - |
| dc.subject.keywordPlus | NAND flash memory | - |
| dc.subject.keywordPlus | Performance requirements | - |
| dc.subject.keywordPlus | Simulation technique | - |
| dc.subject.keywordPlus | Storage systems | - |
| dc.subject.keywordPlus | Technical specifications | - |
| dc.subject.keywordPlus | Verilog hardware description languages | - |
| dc.subject.keywordPlus | Controllers | - |
| dc.subject.keywordAuthor | channel controller | - |
| dc.subject.keywordAuthor | NAND flash memory | - |
| dc.subject.keywordAuthor | scalability | - |
| dc.subject.keywordAuthor | storage system | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/6863981 | - |
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