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Analysis of thermal behavior for 3D integration of DRAM
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Youngil | - |
| dc.contributor.author | Song, Yong Ho | - |
| dc.date.accessioned | 2024-12-20T06:24:13Z | - |
| dc.date.available | 2024-12-20T06:24:13Z | - |
| dc.date.issued | 2014-06 | - |
| dc.identifier.issn | 0000-0000 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/202722 | - |
| dc.description.abstract | The TSV-based 3D integration is a promising technique to improve the chip integration density and increase memory bandwidth. When memories dies are stacked, they are placed on top of a multi-core die. However, the heat dissipated by a die is propagated to neighboring dies and thus increase their temperature. The increased power density in a 3D integration often causes thermal issue to be critical. Therefore, analysis of thermal behavior for 3D integration is essential for solving thermal issue. In this paper, we present our analysis results of the thermal characteristic of various 3D integration techniques. | - |
| dc.format.extent | 2 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.title | Analysis of thermal behavior for 3D integration of DRAM | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.doi | 10.1109/ISCE.2014.6884440 | - |
| dc.identifier.scopusid | 2-s2.0-84907394096 | - |
| dc.identifier.bibliographicCitation | Proceedings of the International Symposium on Consumer Electronics, ISCE, pp 1 - 2 | - |
| dc.citation.title | Proceedings of the International Symposium on Consumer Electronics, ISCE | - |
| dc.citation.startPage | 1 | - |
| dc.citation.endPage | 2 | - |
| dc.type.docType | Conference Paper | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.subject.keywordPlus | Consumer electronics | - |
| dc.subject.keywordPlus | Dies | - |
| dc.subject.keywordPlus | Dynamic random access storage | - |
| dc.subject.keywordPlus | Microprocessor chips | - |
| dc.subject.keywordPlus | Thermoanalysis | - |
| dc.subject.keywordPlus | 3-D integration | - |
| dc.subject.keywordPlus | Chip integration density | - |
| dc.subject.keywordPlus | L2 Cache | - |
| dc.subject.keywordPlus | Memory bandwidths | - |
| dc.subject.keywordPlus | Multi core | - |
| dc.subject.keywordPlus | Power densities | - |
| dc.subject.keywordPlus | Thermal behaviors | - |
| dc.subject.keywordPlus | Thermal characteristics | - |
| dc.subject.keywordPlus | Three dimensional integrated circuits | - |
| dc.subject.keywordAuthor | 3D IC | - |
| dc.subject.keywordAuthor | L2 cache | - |
| dc.subject.keywordAuthor | Microprocessor | - |
| dc.subject.keywordAuthor | Thermal analysis | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/6884440 | - |
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