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Selective restart of threads for efficient thread-level speculation on multicore architecture

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dc.contributor.authorLee, Sungjae-
dc.contributor.authorLee, Inhwan-
dc.date.accessioned2024-12-20T06:30:07Z-
dc.date.available2024-12-20T06:30:07Z-
dc.date.issued2012-02-
dc.identifier.issn1349-2543-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/202936-
dc.description.abstractAn efficient recovery method for thread-level speculation (TLS) is proposed. The method tracks the inter-thread data dependence as a method for identifying those threads that are obviously unaffected by a data dependence violation. The method is simple to implement. Still, the simulation results using benchmark applications show that the method can significantly reduce the number of unnecessary thread restarts and consequently improve the performance of TLS. Specifically, when compared with the baseline TLS, TLS with the proposed method is 2.3 times faster for IS, 1.7 times faster for equake, and 3.5 times faster for mcf with the use of 64 cores. With the method, the performance of TLS increases steadily up to 64 cores for IS, equake, and mcf, while the speedup of the baseline TLS starts to saturate at 8 or 16 cores.-
dc.format.extent6-
dc.language영어-
dc.language.isoENG-
dc.publisherThe Institute of Electronics, Information and Communication Engineers (IEICE)-
dc.titleSelective restart of threads for efficient thread-level speculation on multicore architecture-
dc.typeArticle-
dc.publisher.location일본-
dc.identifier.doi10.1587/elex.9.290-
dc.identifier.scopusid2-s2.0-84863298350-
dc.identifier.wosid000303252300014-
dc.identifier.bibliographicCitationIEICE Electronics Express, v.9, no.4, pp 290 - 295-
dc.citation.titleIEICE Electronics Express-
dc.citation.volume9-
dc.citation.number4-
dc.citation.startPage290-
dc.citation.endPage295-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusSoftware architecture-
dc.subject.keywordAuthormulticore architecture-
dc.subject.keywordAuthorthread-level speculation-
dc.subject.keywordAuthorselective restart-
dc.identifier.urlhttps://www.jstage.jst.go.jp/article/elex/9/4/9_4_290/_article-
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서울 공과대학 > 서울 컴퓨터소프트웨어학부 > 1. Journal Articles

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