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Selective restart of threads for efficient thread-level speculation on multicore architecture
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, Sungjae | - |
| dc.contributor.author | Lee, Inhwan | - |
| dc.date.accessioned | 2024-12-20T06:30:07Z | - |
| dc.date.available | 2024-12-20T06:30:07Z | - |
| dc.date.issued | 2012-02 | - |
| dc.identifier.issn | 1349-2543 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/202936 | - |
| dc.description.abstract | An efficient recovery method for thread-level speculation (TLS) is proposed. The method tracks the inter-thread data dependence as a method for identifying those threads that are obviously unaffected by a data dependence violation. The method is simple to implement. Still, the simulation results using benchmark applications show that the method can significantly reduce the number of unnecessary thread restarts and consequently improve the performance of TLS. Specifically, when compared with the baseline TLS, TLS with the proposed method is 2.3 times faster for IS, 1.7 times faster for equake, and 3.5 times faster for mcf with the use of 64 cores. With the method, the performance of TLS increases steadily up to 64 cores for IS, equake, and mcf, while the speedup of the baseline TLS starts to saturate at 8 or 16 cores. | - |
| dc.format.extent | 6 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | The Institute of Electronics, Information and Communication Engineers (IEICE) | - |
| dc.title | Selective restart of threads for efficient thread-level speculation on multicore architecture | - |
| dc.type | Article | - |
| dc.publisher.location | 일본 | - |
| dc.identifier.doi | 10.1587/elex.9.290 | - |
| dc.identifier.scopusid | 2-s2.0-84863298350 | - |
| dc.identifier.wosid | 000303252300014 | - |
| dc.identifier.bibliographicCitation | IEICE Electronics Express, v.9, no.4, pp 290 - 295 | - |
| dc.citation.title | IEICE Electronics Express | - |
| dc.citation.volume | 9 | - |
| dc.citation.number | 4 | - |
| dc.citation.startPage | 290 | - |
| dc.citation.endPage | 295 | - |
| dc.type.docType | Article | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.subject.keywordPlus | Software architecture | - |
| dc.subject.keywordAuthor | multicore architecture | - |
| dc.subject.keywordAuthor | thread-level speculation | - |
| dc.subject.keywordAuthor | selective restart | - |
| dc.identifier.url | https://www.jstage.jst.go.jp/article/elex/9/4/9_4_290/_article | - |
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