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Dynamic Rate Neural Acceleration Using Multiprocessing Mode Support

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dc.contributor.authorLee, Inho-
dc.contributor.authorLee, Yangki-
dc.contributor.authorUm, Hongjun-
dc.contributor.authorHong, Seongmin-
dc.contributor.authorPark, Yongjun-
dc.date.accessioned2024-12-20T07:27:44Z-
dc.date.available2024-12-20T07:27:44Z-
dc.date.issued2022-10-
dc.identifier.issn1063-8210-
dc.identifier.issn1557-9999-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/203522-
dc.description.abstractMultiobject detection has become an integral component in various neural applications, such as autonomous driving and augmented reality. The system should be able to recognize and process multiple objects simultaneously. Moreover, the performance requirements for this system can be dynamically changed depending on the number of regions of interest (ROIs) in each frame. Consequently, the processing unit (PU) of the neural acceleration system should provide various inference rates. Therefore, we present a field-programmable gate array (FPGA)-based dynamic rate neural acceleration system called MultiLockOn to dynamically change the inference performance according to the number of ROIs per frame. It supports multiprocessing modes with different speeds through the introduction of novel multi-mode processing engines (PEs) comprising minimum reconfigurable interconnections across inference modes to minimize hardware overhead. The MultiLockOn system can provide an improvement of up to 4<inline-formula> <tex-math notation=LaTeX>$\times$</tex-math> </inline-formula> in the inference performance compared to that of DNNWeaver and 5.7<inline-formula> <tex-math notation=LaTeX>$\times$</tex-math> </inline-formula> compared to that of the ARM Cortex-A53 with minimum accuracy loss by supporting the multiprocessing modes.-
dc.format.extent12-
dc.language영어-
dc.language.isoENG-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleDynamic Rate Neural Acceleration Using Multiprocessing Mode Support-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/TVLSI.2022.3178615-
dc.identifier.scopusid2-s2.0-85132750914-
dc.identifier.wosid000861436900012-
dc.identifier.bibliographicCitationIEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.30, no.10, pp 1461 - 1472-
dc.citation.titleIEEE Transactions on Very Large Scale Integration (VLSI) Systems-
dc.citation.volume30-
dc.citation.number10-
dc.citation.startPage1461-
dc.citation.endPage1472-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusLICENSE-PLATE-RECOGNITION-
dc.subject.keywordAuthorAccelerator-
dc.subject.keywordAuthorapproximation-
dc.subject.keywordAuthorneural networks-
dc.subject.keywordAuthorregion of interest (ROI)-
dc.subject.keywordAuthorweight quantization-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/9798879-
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