Design Strategies for BCAT Structures: Enhancing DRAM Reliability and Mitigating Row Hammer Effect

Abstract

This study investigates the impact of four parameters-gate angles, fin height controlled through gate overlaps and the distance from fin to source/drain, and substrate bottom doping concentration-on the row hammer effect (RHE) in DRAM cells. The influence of adjacent and passing gates on the DRAM cell body potential was identified as a key factor in D0 and D1 failures. The tolerance for D1 and D0 failures was analyzed, defined as the threshold number of pulses required to induce a 0.6 V change in the storage node voltage (from 1.2 V to 0.6 V for a D1 failure or from 0 V to 0.6 V for a D0 failure). D1 (D0) failure tolerances with the slope from the top of the top gate (theta angle) of 3 degrees, the height of the TiN gate covering the fin (Hfin_overlap) of 12.5 nm, and the height of the fin (Hfin) of 12.5 nm are 1.26 x 106 (4.8 x 106), 1.14 x 106 (4 x 107), and 7.5 x 105 (4.8 x 105), respectively. Higher theta angles and smaller fin heights generally result in higher RHE tolerances. Although decreasing the fin height reduced the RHE, it also decreased the on-current and resulted in an increase in the threshold voltage (VT) and the subthreshold swing (SS). In addition, by increasing the substrate bottom doping concentration (Pdop_bot), we improve RHE tolerance twice its original level without reducing the on-current. Therefore, designing a buried channel array transistor (BCAT) structure requires careful consideration of these trade-offs, and a thorough understanding of the underlying mechanism is crucial to devising strategies that reduce RHE tolerance. The findings of this study are expected to contribute significantly to the development of next-generation DRAM architectures, enhancing stability and performance. By addressing the reliability challenges posed by advanced scaling, this study paves the way for the ongoing advancement of DRAM technology for high-density and high-performance applications.