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Optimal strategy for mapping spiking neural networks onto manycore neuromorphic processors
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Ye, ChangMin | - |
| dc.contributor.author | Jeong, Doo Seok | - |
| dc.date.accessioned | 2025-08-12T07:00:10Z | - |
| dc.date.available | 2025-08-12T07:00:10Z | - |
| dc.date.issued | 2025-06 | - |
| dc.identifier.issn | 0271-4302 | - |
| dc.identifier.issn | 2158-1525 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/208496 | - |
| dc.description.abstract | Manycore digital neuromorphic event processors execute ad hoc event routing between spiking neurons distributed across multiple cores. Due to limited hardware resources, such as on-chip memory capacity, only a limited number of neurons and their fan-in weights can be accommodated per core. This challenge is particularly significant for convolutional layers, where placing neurons from the same layer in different cores hinders weight reuse, as the same weight must be duplicated across cores. To address this, we propose an optimal mapping method for spiking units across multiple cores, considering hardware resource constraints. This method is based on the discrete Lagrange Multiplier Method, which uses a total memory usage as an objective function alongside constraint functions (memory usage per core). Our results show that this method achieves optimal spiking unit distributions with high core memory utilization (> 70%) for the reduced ResNet models. | - |
| dc.format.extent | 5 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.title | Optimal strategy for mapping spiking neural networks onto manycore neuromorphic processors | - |
| dc.type | Article | - |
| dc.publisher.location | 영국 | - |
| dc.identifier.doi | 10.1109/ISCAS56072.2025.11043287 | - |
| dc.identifier.scopusid | 2-s2.0-105010620941 | - |
| dc.identifier.bibliographicCitation | IEEE International Symposium on Circuits and Systems proceedings, pp 1 - 5 | - |
| dc.citation.title | IEEE International Symposium on Circuits and Systems proceedings | - |
| dc.citation.startPage | 1 | - |
| dc.citation.endPage | 5 | - |
| dc.type.docType | Conference paper | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.subject.keywordPlus | Computer hardware | - |
| dc.subject.keywordPlus | Distributed computer systems | - |
| dc.subject.keywordPlus | Mapping | - |
| dc.subject.keywordPlus | Multiplying circuits | - |
| dc.subject.keywordPlus | Neural networks | - |
| dc.subject.keywordPlus | Neurons | - |
| dc.subject.keywordAuthor | Largrange multiplier method | - |
| dc.subject.keywordAuthor | manycore neuromorphic processor | - |
| dc.subject.keywordAuthor | spiking neural network mapping | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/11043287 | - |
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