A Reconfigurable Bidirectional Wireless Power and Full-Duplex Data Transceiver IC for Wearable Biomedical Applications
- Authors
- Lee, Junhyuck; Kim, Yemin; Kang, Dongil; Song, Ickhyun; Lee, Byunghun
- Issue Date
- Aug-2025
- Publisher
- Institute of Electrical and Electronics Engineers
- Keywords
- Data communication; Wireless communication; Uplink; Transceivers; Downlink; Frequency shift keying; Wireless sensor networks; Full-duplex system; Biomedical monitoring; Wearable devices; Wireless power transfer (WPT); wireless power and data transfer (WPDT); reconfigurable transceiver; full-duplex (FD) data transmission; bidirectional wireless power and data transfer; inductive link, wearable device
- Citation
- IEEE Transactions on Biomedical Circuits and Systems, v.19, no.4, pp 767 - 776
- Pages
- 10
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE Transactions on Biomedical Circuits and Systems
- Volume
- 19
- Number
- 4
- Start Page
- 767
- End Page
- 776
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/210012
- DOI
- 10.1109/TBCAS.2024.3483950
- ISSN
- 1932-4545
1940-9990
- Abstract
- This paper presents a reconfigurable bidirectional wireless power and data transceiver (RB-WPDT) integrated circuit (IC) for wearable biomedical applications. The proposed transceiver can be reconfigured as a differential class-D power amplifier or a full-wave rectifier depending on the mode signal to facilitate power transfer between devices. Additionally, the RBWPDT system supports full-duplex (FD) data transmission via a single inductive link, enabling real-time control and monitoring between devices. The proposed FD method utilizes frequency shift-keying pulse-width modulation (FSK-PWM) for downlink and load shift-keying (LSK) for uplink, achieving simultaneous bidirectional data transmission by ensuring that the FSK-PWM downlink and LSK uplink data channels operate independently with minimal interference. The measured downlink and uplink data rates are 250 kb/s and 67 kb/s, respectively. The measured overall DC-to-DC efficiency is 49%, while the power delivered to the load (PDL) is 120 mW at a 5 mm distance. The proposed chip is fabricated using a 180-nm BCD CMOS process.
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