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An Inductive Loading Simultaneous Noise and Input Matching Technique with Current Reuse for Low-Power LNA

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dc.contributor.authorHuynh, Phuoc B. T.-
dc.contributor.authorLee, Gyeong-Seok-
dc.contributor.authorPark, Jun-Young-
dc.contributor.authorYun, Tae-Yeoul-
dc.date.accessioned2026-01-23T06:30:37Z-
dc.date.available2026-01-23T06:30:37Z-
dc.date.issued2025-07-
dc.identifier.issn0018-9200-
dc.identifier.issn1558-173X-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/210455-
dc.description.abstractThis article presents an inductive loading simultaneous noise and input matching (ILSNIM) technique for a low-power low-noise amplifier (LNA). In contrast to conventional simultaneous noise and input matching (SNIM) methods, where lossy resistance associated with an on-chip low-Q gate inductor substantially degrades the total noise figure (NF) performance, the input stage of the proposed LNA exploits the gate-drain capacitance feedback incorporated with inductive loading for the first time to construct the input impedance network. This design approach overcomes the NF limitation in conventional SNIM techniques by eliminating the lossy gate inductor while boosting the transconductance to achieve SNIM under low power consumption. Furthermore, a current-reuse structure with a cascaded stage is applied not only to enhance the overall gain but also to generate a noiseless resistive component that addresses the instability issue without adverse impacts on other performances. Fabricated using a 0.11- μm complementary metal-oxide-semiconductor (CMOS) process, the proposed ILSNIM LNA demonstrates a gain of 13.6 dB, an NF of 2.8 dB, and a third-order input intercept point (IIP3) of - 5.2 dBm at 6.8 GHz under a 1.2-mW power dissipation from a 1-V supply.-
dc.format.extent12-
dc.language영어-
dc.language.isoENG-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleAn Inductive Loading Simultaneous Noise and Input Matching Technique with Current Reuse for Low-Power LNA-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/JSSC.2024.3511578-
dc.identifier.scopusid2-s2.0-85212279926-
dc.identifier.wosid001377365600001-
dc.identifier.bibliographicCitationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.60, no.7, pp 2461 - 2472-
dc.citation.titleIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.citation.volume60-
dc.citation.number7-
dc.citation.startPage2461-
dc.citation.endPage2472-
dc.type.docTypeArticle in press-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusCMOS LNA-
dc.subject.keywordPlusAMPLIFIER-
dc.subject.keywordPlusOPTIMIZATION-
dc.subject.keywordPlusSUBSTRATE-
dc.subject.keywordPlusDESIGN-
dc.subject.keywordPlusFIGURE-
dc.subject.keywordPlusDB-
dc.subject.keywordPlusESD-
dc.subject.keywordAuthorLogic gates-
dc.subject.keywordAuthorImpedance-
dc.subject.keywordAuthorNoise-
dc.subject.keywordAuthorLoading-
dc.subject.keywordAuthorResistance-
dc.subject.keywordAuthorNoise measurement-
dc.subject.keywordAuthorInductors-
dc.subject.keywordAuthorImpedance matching-
dc.subject.keywordAuthorCapacitance-
dc.subject.keywordAuthorTransconductance-
dc.subject.keywordAuthorCapacitive loading simultaneous noise and input matching (CLSNIM)-
dc.subject.keywordAuthorinductive loading SNIM (ILSNIM)-
dc.subject.keywordAuthorpower constrained SNIM (PCSNIM)-
dc.subject.keywordAuthorsimultaneous noise and input matching (SNIM)-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/10787398-
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