Coupling-Free Readout Scheme for Memcapacitors With NAND Flash Structure

Abstract

In this article, we propose a coupling-free readout scheme designed for a hardware neural network employing memcapacitive devices based on Si MOS capacitors having a charging trapping layer. The capacitance of each device can be adjusted with the threshold voltage modulation by program and erase operations. Since the array structure is based on NAND flash array, memcapacitive devices share gate and substrate electrodes, so capacitive coupling effects can arise from unselected devices during readout operations with charging and discharging behaviors. Our proposed readout scheme addresses this issue by grounding both ends of the unselected cell, thereby mitigating the issue of additional bitline (BL) charge accumulation caused by coupling effects. The TCAD simulations are also conducted to validate the effectiveness of the readout scheme, and accurate vector-matrix multiplication (VMM) operations are experimentally verified with a 32 x 32 fabricated memcapacitor crossbar array. Also, a neuron circuit is experimentally verified by connecting to the capacitive devices. Based on the measurement results, the accurate VMM operations in a 3-D memcapacitor array structure based on wordline (WL)-stacked 3-D NAND flash are also confirmed by the SPICE studies.