Ferroelectric Memcapacitor Crossbar Array with NAND Flash Structure for In-Memory Computing

Abstract

In this paper, 48×24 ferroelectric memcapacitor crossbar is experimentally demonstrated based on NAND flash structure, with TiN/HZO/SiO2/poly-Si gate stack. With the optimal read voltage, a wide charge memory window of ~12.27 fC/μm2 is achieved. Read, write, and inhibit operations are successfully verified across the fabricated array, enabling reliable 4-bit multilevel programming with retention over 10 years. Vector-matrix multiplication operations are confirmed with an R2 value of 0.984, with the verification of output sensing circuit. Also, CIFAR-10 classification is implemented on the fabricated 48×24 array by pretrained weight transfer with 4-bit device states, achieving accuracy of 87.75%. The feasibility of vertically stacked structure based on 3D-NAND flash is also verified by TCAD and SPICE simulations.