A compact model for SiGe heterojunction bipolar transistor under AC-stress conditionsopen access
- Authors
- Kim, Taeyeong; Kang, Kyubeom; Lee, Jongho; Jeong, Junhwa; Oakley, Michael A.; Cho, Moon-Kyu; Cressler, John D.; Lee, Byunghun; Song, Ickhyun
- Issue Date
- Jun-2026
- Publisher
- Elsevier B.V.
- Keywords
- AC stress; Avalanche breakdown; Degradation modeling; Electrical stress; Heterojunction bipolar transistor (HBT); High-frequency amplifier; Silicon germanium (SiGe)
- Citation
- Results in Physics, v.85, pp 1 - 9
- Pages
- 9
- Indexed
- SCOPUS
- Journal Title
- Results in Physics
- Volume
- 85
- Start Page
- 1
- End Page
- 9
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/212946
- DOI
- 10.1016/j.rinp.2026.108677
- ISSN
- 2211-3797
- Abstract
- This paper presents a compact model of AC-stress-induced performance degradation in silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) high-frequency amplifiers for circuit-level simulations. The proposed model introduces additional diode, resistor, and inductor to existing design-kit model to represent stress-induced base leakage and high-frequency degradation, enabling the analysis of base leakage current, current gain (β), cutoff frequency (fT), maximum oscillation frequency (fmax), impedance variation, and RF performance degradation under large-signal AC stress. The model was validated using two amplifier samples fabricated in GlobalFoundries 130 nm SiGe BiCMOS technology. Under AC stress, both samples exhibited similar RF degradation trends, including reduced power gain, while additional measurements on the second sample confirmed increased base current and reduced current gain after stress. In addition, simulation results showed degradation trends in fT and fmax together with shifts associated with the stress-induced increase in base current. The proposed model reproduced the measured degradation behavior and can be directly implemented in standard design-kit-based simulation environment. These results demonstrate that the proposed approach provides a practical framework for predicting and analyzing AC-stress-induced degradation at both the device and circuit levels.
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