Thermal Impact of TSV Misalignment and Micro-Bump Height in 3D IC Packages

Abstract

In high-performance Three-dimensional integrated circuits (3D-IC) packages such as HBM, TSVs (Through-Silicon Vias) function not only as electrical interconnects but also as key vertical heat conduction paths. This study performs FEM-based thermal simulations to analyze the impact of TSV misalignment on the thermal behavior of stacked die structures. In addition, the effect of varying μ-bump height on vertical heat dissipation is quantitatively evaluated under realistic package conditions. Simulation results show that both TSV misalignment and increased bump height degrade thermal performance, leading to higher maximum temperatures in the dies. These findings provide valuable insights for establishing thermal design guidelines in 3D IC layout and manufacturing.