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Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Hyun, Jinhoon | - |
| dc.contributor.author | Jeong, Inchul | - |
| dc.contributor.author | Chu, Shinho | - |
| dc.contributor.author | Lim, Jaemyung | - |
| dc.date.accessioned | 2026-06-22T05:00:25Z | - |
| dc.date.available | 2026-06-22T05:00:25Z | - |
| dc.date.issued | 2026-04 | - |
| dc.identifier.issn | 0278-0070 | - |
| dc.identifier.issn | 1937-4151 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/213963 | - |
| dc.description.abstract | In modern DRAM design, IR-drop has emerged as a critical factor leading to operation failures, primarily due to reduced metal resources and increased supply current demands. Consequently, estimating and addressing IR-drop throughout the DRAM design process has become a crucial sign-off consideration. The proposed comprehensive methodology for the power delivery network (PDN) includes accurate and efficient estimation at two key stages: early in the design process (Early PDN) and during post-physical design sign-off validation (Iterative PDN). The Early PDN approach employs simplified modeling to achieve reasonable accuracy, serving as a guideline for the initial PDN design. Subsequently, the Iterative PDN method provides a fast yet detailed analysis of the entire DRAM, including the PDN, ensuring it is suitable for final sign-off. By applying this methodology, PDN behavior can be effectively predicted and optimized, ensuring robustness. This enhances the reliability and performance of DRAM designs. | - |
| dc.format.extent | 5 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
| dc.title | Comprehensive PDN Methodology for DRAM: Early PDN and Iterative PDN | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.doi | 10.1109/TCAD.2025.3607129 | - |
| dc.identifier.scopusid | 2-s2.0-105015415959 | - |
| dc.identifier.wosid | 001723877500005 | - |
| dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.45, no.4, pp 1782 - 1786 | - |
| dc.citation.title | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
| dc.citation.volume | 45 | - |
| dc.citation.number | 4 | - |
| dc.citation.startPage | 1782 | - |
| dc.citation.endPage | 1786 | - |
| dc.type.docType | Article | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Computer Science | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
| dc.relation.journalWebOfScienceCategory | Computer Science, Interdisciplinary Applications | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.subject.keywordPlus | Computer aided design | - |
| dc.subject.keywordPlus | Dynamic random access storage | - |
| dc.subject.keywordPlus | Electric power transmission | - |
| dc.subject.keywordPlus | Integrated circuit design | - |
| dc.subject.keywordPlus | Logic design | - |
| dc.subject.keywordPlus | Reliability | - |
| dc.subject.keywordAuthor | Random access memory | - |
| dc.subject.keywordAuthor | Metals | - |
| dc.subject.keywordAuthor | Iterative methods | - |
| dc.subject.keywordAuthor | Circuits | - |
| dc.subject.keywordAuthor | Voltage measurement | - |
| dc.subject.keywordAuthor | Integrated circuit modeling | - |
| dc.subject.keywordAuthor | Computer architecture | - |
| dc.subject.keywordAuthor | Estimation | - |
| dc.subject.keywordAuthor | Microprocessors | - |
| dc.subject.keywordAuthor | Computational modeling | - |
| dc.subject.keywordAuthor | DRAM power integrity | - |
| dc.subject.keywordAuthor | high-bandwidth memory (HBM) | - |
| dc.subject.keywordAuthor | IR-drop | - |
| dc.subject.keywordAuthor | on-chip power delivery network (PDN) | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/11153455 | - |
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