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Optimized Memory System Architecture for VESA VDC-M Decoder with Multi-Slice Support
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 김지훈 | - |
| dc.date.accessioned | 2026-06-25T17:31:40Z | - |
| dc.date.available | 2026-06-25T17:31:40Z | - |
| dc.date.issued | 2025-05-26 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/217396 | - |
| dc.title | Optimized Memory System Architecture for VESA VDC-M Decoder with Multi-Slice Support | - |
| dc.type | Conference | - |
| dc.citation.conferenceName | IEEE ISCAS (International Symposium on Circuits and Systems) | - |
| dc.citation.conferencePlace | InterContinental London The O2 | - |
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Collections - 서울 공과대학 > 서울 융합전자공학부 > 2. Conference Papers
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Related Researcher
- Kim, Ji Hoon
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)