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RISC-V Integrated Nested Loop Analyzer for Runtime DRAM Test Pattern Generation
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 김지훈 | - |
| dc.date.accessioned | 2026-06-25T17:31:49Z | - |
| dc.date.available | 2026-06-25T17:31:49Z | - |
| dc.date.issued | 2025-09-29 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/217402 | - |
| dc.title | RISC-V Integrated Nested Loop Analyzer for Runtime DRAM Test Pattern Generation | - |
| dc.type | Conference | - |
| dc.citation.conferenceName | CODES+ISSS 2025 | - |
| dc.citation.conferencePlace | Taipei International Convention Center (TICC) | - |
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Related Researcher
- Kim, Ji Hoon
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)