A Gate-All-Around Back-Gated Junctionless 3D NAND Structure for Improved Switching Efficiency and Variability Suppression

Abstract

As 3D NAND technology scales vertically to ultrahigh layer counts, cell current degradation caused by the low mobility of poly-silicon channels has emerged as a critical bottleneck. Junctionless (JL) devices employing heavily doped channels have been introduced to boost cell current through bulk conduction. However, such devices suffer from degraded cut-off characteristics and increased threshold voltage (Vth) variability due to random dopant fluctuation (RDF) and grain boundary segregation. In this paper, we propose a gate-allaround with back-gate (GAAB) junctionless 3D NAND structure to address these limitations. By introducing a backside control gate in planar test devices, we experimentally demonstrate that applying a negative back-bias induces a virtual thin-body effect. This effect effectively suppresses backchannel leakage and improves the subthreshold swing (SS), while preserving the high current drive capability of the junctionless channel. Furthermore, 3D TCAD simulations on a 64-word-line string confirm that the proposed structure significantly enhances switching efficiency and reduces variability compared with conventional schemes, offering a robust solution for ultra-high stack 3D NAND technology.