Design of Robust Clock-Tree Circuit with Transient-Recovery Technique

Abstract

This paper explores various circuit designs aimed at mitigating single-event effects (SEE) in integrated circuits (ICs). The proposed designs exhibit improved reliability from transient errors due to high-energy particles in space or radiation-intense environment. In this work, the strengths and weaknesses of conventional circuits against soft errors are discussed. Then, the proposed circuit designs including timedelay and feedback loop are presented to provide improved signal recovery at both input and output terminals. In addition, the proposed topologies can reduce the impact of SEE at both of logic-1 and 0 signals. Designed in a 28-nm CMOS process, the proposed circuit demonstrates a dynamic power of 0.036 pW/cycle and a leakage power of 0.09 μ W. It exhibits significant improvements in robustness against soft errors, thereby reducing potential data distortion or corruption.