Skew cancellation technique for > 256-Gbyte/s high-bandwidth memory (HBM)

Abstract

The skews among multi-Gbit/s data signals of through-silicon-via-based parallel DRAM interface are cancelled without any overhead on DRAM dies. All the skew cancelling circuits are realised on a logic die which cancels the write and read path skews separately. A prototype chip with the proposed skew cancellation has been implemented in a 65 nm standard CMOS technology. After the skew cancellation, the residual skew of read and write paths are 12 and 18 ps, respectively.