Bit Error Floor of MPSK in the Presence of Phase Error
- Authors
- Jang, Yeonsoo; Jeong, Jinwoo; Yoon, Dongweon
- Issue Date
- May-2016
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Bit error floor; channel estimation; M-ary phase-shift keying (MPSK); phase error; phase-locked loop (PLL)
- Citation
- IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, v.65, no.5, pp.3782 - 3786
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY
- Volume
- 65
- Number
- 5
- Start Page
- 3782
- End Page
- 3786
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/23110
- DOI
- 10.1109/TVT.2015.2437792
- ISSN
- 0018-9545
- Abstract
- In mobile communication systems, one of the most significant factors of the bit-error-rate (BER) performance degradation of M-ary phase-shift keying (MPSK) is random phase error caused by phase-locked loop (PLL) or imperfect channel estimation. For high-signal-to-noise-power-ratio (SNR) regions, the effect of random phase error on BER performance becomes dominant and results in an irreducible BER called the bit error floor. In this paper, we derive a bit error floor expression of Gray-coded MPSK when random phase error exists and show that the bit error floor in fading channels converges to the bit error floor in additive white Gaussian noise (AWGN) channels. The derived expression is simple and accurate in the error floor region; hence, it can offer a convenient way to calculate the irreducible BER of MPSK in the presence of phase error.
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