Cited 2 time in
UIBF decoding to lower the error floors of high-rate systematic LDPC codes
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lim, Jinsoo | - |
| dc.contributor.author | Shin, Dongjoon | - |
| dc.date.accessioned | 2021-07-30T05:04:48Z | - |
| dc.date.available | 2021-07-30T05:04:48Z | - |
| dc.date.issued | 2017-02 | - |
| dc.identifier.issn | 0013-5194 | - |
| dc.identifier.issn | 1350-911X | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/2779 | - |
| dc.description.abstract | An unreliability-based information bit flipping (UIBF) decoding using cyclic redundancy check is proposed to lower the error floors of high-rate systematic low-density parity-check (LDPC) codes. Unsuccessfully decoded codeword is redecoded by the UIBF decoding with very low complexity at the end of every iteration of the sum-product (SP) decoding. The proposed scheme is applied to LDPC codes of the IEEE 802.16e standard. Simulation results show that the proposed scheme effectively lowers the error floors of systematic LDPC codes with smaller number of iterations compared with the conventional SP decoding scheme, which leads to the reduced power consumption and increased data throughput. | - |
| dc.format.extent | 3 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | Institute of Electrical Engineers | - |
| dc.title | UIBF decoding to lower the error floors of high-rate systematic LDPC codes | - |
| dc.type | Article | - |
| dc.publisher.location | 영국 | - |
| dc.identifier.doi | 10.1049/el.2016.2827 | - |
| dc.identifier.scopusid | 2-s2.0-85013634660 | - |
| dc.identifier.wosid | 000395555400023 | - |
| dc.identifier.bibliographicCitation | Electronics Letters, v.53, no.4, pp 247 - 249 | - |
| dc.citation.title | Electronics Letters | - |
| dc.citation.volume | 53 | - |
| dc.citation.number | 4 | - |
| dc.citation.startPage | 247 | - |
| dc.citation.endPage | 249 | - |
| dc.type.docType | Article | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | sci | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.subject.keywordAuthor | parity check codes | - |
| dc.subject.keywordAuthor | iterative decoding | - |
| dc.subject.keywordAuthor | UIBF decoding | - |
| dc.subject.keywordAuthor | error floors | - |
| dc.subject.keywordAuthor | high-rate systematic LDPC codes | - |
| dc.subject.keywordAuthor | unreliability based information bit flipping | - |
| dc.subject.keywordAuthor | cyclic redundancy check | - |
| dc.subject.keywordAuthor | decoded codeword | - |
| dc.subject.keywordAuthor | sum product decoding | - |
| dc.subject.keywordAuthor | SP decoding | - |
| dc.subject.keywordAuthor | IEEE 802 | - |
| dc.subject.keywordAuthor | 16e standard | - |
| dc.subject.keywordAuthor | SP decoding scheme | - |
| dc.identifier.url | https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/el.2016.2827 | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
222, Wangsimni-ro, Seongdong-gu, Seoul, 04763, Korea+82-2-2220-1366
COPYRIGHT © 2024 HANYANG UNIVERSITY.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.
