Pointer Based Routing Scheme for On-chip Learning in Neuromorphic Systems

Abstract

A look-up table (LUT)-based spike-routing approach is often used in inference-only neuromorphic systems due to its excellent reconfigurability. The challenge is to apply this approach also to on-chip learning that requires a search of a lengthy LUT for all relevant synapses to a firing neuron. To solve this issue, we propose a pointer-based routing scheme that remarkably accelerates spike-routing at the cost of an additional LUT (pointer LUT). Our theoretical estimations suggest that the proposed routing scheme at 1 GHz clock speed supports a spiking neural network of up to 10⁷ synapses and more than 10⁵ neurons firing at 50 Hz without spike traffic congestion. The scheme needs approximately 32 MB memory. To verify experimentally, the proposed routing scheme was implemented on a Xilinx Virtex 7 FPGA board deploying an array of leaky integrate-and-fire neurons.