Detailed Information
Cited 0 time in 
Cited 0 time in 
Cited 0 time in
Metadata Downloads
Two-terminal Vertical Thyristor-based Capacitor-less Memory Cells Using Latch-up Features
Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 박재근 | - |
| dc.date.accessioned | 2021-08-03T02:27:52Z | - |
| dc.date.available | 2021-08-03T02:27:52Z | - |
| dc.date.issued | 2017-05-25 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/32326 | - |
| dc.title | Two-terminal Vertical Thyristor-based Capacitor-less Memory Cells Using Latch-up Features | - |
| dc.type | Conference | - |
| dc.citation.conferenceName | ULSIC vs TFT: 6th International Conference on Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film Transistors | - |
| dc.citation.conferencePlace | Schloss Hernstein | - |
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - 서울 공과대학 > 서울 융합전자공학부 > 2. Conference Papers
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.