Cited 5 time in
Hierarchical Dataflow Modeling of Iterative Applications
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Hong, Hyesun | - |
| dc.contributor.author | Oh, Hyunok | - |
| dc.contributor.author | Ha, Soonhoi | - |
| dc.date.accessioned | 2021-08-03T03:27:31Z | - |
| dc.date.available | 2021-08-03T03:27:31Z | - |
| dc.date.issued | 2017-06 | - |
| dc.identifier.issn | 0738-100X | - |
| dc.identifier.issn | 0146-7123 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/33026 | - |
| dc.description.abstract | Even though dataflow models are good at exploiting task-level parallelism of an application, it is difficult to exploit the parallelism of loop structures since they are not explicitly specified in existent dataflow models. To overcome this drawback, we propose a novel extension to the SDF model, called SDF/L graph, specifying the loop structures explicitly in a hierarchical fashion. With a given SDF/L graph specification and the mapping and scheduling information, an application can be automatically parallelized on a multicore system. The enhanced expression capability by the proposed extension is verified with two applications, k-means clustering and deep neural network application. | - |
| dc.format.extent | 6 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.title | Hierarchical Dataflow Modeling of Iterative Applications | - |
| dc.type | Article | - |
| dc.identifier.doi | 10.1145/3061639.3062260 | - |
| dc.identifier.scopusid | 2-s2.0-85023642707 | - |
| dc.identifier.bibliographicCitation | Proceedings - Design Automation Conference, v.Part 128280, pp 1 - 6 | - |
| dc.citation.title | Proceedings - Design Automation Conference | - |
| dc.citation.volume | Part 128280 | - |
| dc.citation.startPage | 1 | - |
| dc.citation.endPage | 6 | - |
| dc.type.docType | Conference Paper | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.subject.keywordPlus | Computer aided design | - |
| dc.subject.keywordPlus | Deep neural networks | - |
| dc.subject.keywordPlus | Code Generation | - |
| dc.subject.keywordPlus | Dataflow | - |
| dc.subject.keywordPlus | Loop parallelization | - |
| dc.subject.keywordPlus | Multi-core systems | - |
| dc.subject.keywordPlus | Neural network application | - |
| dc.subject.keywordPlus | Scheduling information | - |
| dc.subject.keywordPlus | SDF graph | - |
| dc.subject.keywordPlus | Task level parallelisms | - |
| dc.subject.keywordPlus | Data flow analysis | - |
| dc.subject.keywordAuthor | Code generation | - |
| dc.subject.keywordAuthor | Dataflow | - |
| dc.subject.keywordAuthor | Loop parallelization | - |
| dc.subject.keywordAuthor | SDF graph | - |
| dc.identifier.url | https://dl.acm.org/doi/10.1145/3061639.3062260 | - |
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