Design of memory efficient FIFO-based merge sorter

Abstract

Sorting is an important operation used in various applications including image processing and databases. It represents a large portion of the total execution time of these applications. To improve the performance of sort operations, a dedicated hardware sorter can be used. When implemented in hardware, a FIFO-based merge sorters often shows excellent hardware resource utilization efficiency but requires high buffer memory usage. In this paper, we presents a cost-effective hardware architecture of a FIFO-based merge sorter. Our proposed architecture minimizes buffer memory requirement. We evaluate the design by implementing the architecture on an FPGA platform. FPGA synthesis results show that the proposed approach reduces the average flip-flop and LUT-RAM by 5% and 14%, respectively.