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Physical Modeling for Program speed of SONOS cells with 3D Gate-All-Around (GAA) Charge Trap Memories

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dc.contributor.author송윤흡-
dc.date.accessioned2021-08-03T11:21:19Z-
dc.date.available2021-08-03T11:21:19Z-
dc.date.issued2013-11-01-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/46140-
dc.titlePhysical Modeling for Program speed of SONOS cells with 3D Gate-All-Around (GAA) Charge Trap Memories-
dc.typeConference-
dc.citation.conferenceNameThe 14th International Conference on Computers, Communications and Systems-
dc.citation.conferencePlace대구대학교-
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서울 공과대학 > 서울 융합전자공학부 > 2. Conference Papers

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