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Fabrication of NiSi2 nanocrystal charge storage layer on Si-Fin for nonvolatile memory application

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dc.contributor.author이승백-
dc.date.accessioned2021-08-03T23:22:01Z-
dc.date.available2021-08-03T23:22:01Z-
dc.date.issued2008-08-29-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/64005-
dc.description.abstractDue to ever increasing demand for scaling, non-volatile memory structures need to operate at much reduced current ranges. The 3-dimentional fin-shaped channel structure of a FinFET can relieve the scale down limits with higher device currents compared to the planar MOSFET structures. Here, we report on the charge storage characteristics of nanoscale-floating gate memory (NFGM) with NiSi2 nanocrystals (NCs) formed on the surface of a Si Fin, constituting the nanoscale-floating gate of a FinFET type non-volatile memory. We fabricated fin-type MOS structures (a) with NiSi2 NCs on p-type silicon Fin and planar-type MOS structures (b) with NiSi2 NCs. The Si-fins were fabricated by spacer etching process. An SiO2 sacrificial block was deposited and etched, and Si3N4 spacer was deposited and etched, leaving Si3N4 spacer hard mask structures to be used for the Si reactive ion etching. On the Si-Fin (~40 nm in width and ~200 nm in height) and the Si wafer, SiO2/NiSi2/SiO2 layers were deposited by sputtering a commixed target at room temperature. Then rapid thermal annealing process was performed in N2 ambient at 800°C for 180 sec, which resulted in the formation of 3-nm diameter NiSi2 NCs. The charge storage characteristics of Fin-type sample and planar-type sample were compared by CV hysteresis tests and showed that the FinFET type NFGM showed higher capacitance with similar reliability characteristics compared to the MOS type NFGM-
dc.titleFabrication of NiSi2 nanocrystal charge storage layer on Si-Fin for nonvolatile memory application-
dc.typeConference-
dc.citation.conferenceNameThe 14th International Symposium on the Physics of Semiconductors and Applications-
dc.citation.conferencePlaceJeju, Korea-
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서울 공과대학 > 서울 융합전자공학부 > 2. Conference Papers

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