Formation of double layer NiSi2 nanocrystals for nonvolatile memory application

Abstract

Due to the continuing scaling of nanoscale memory devices, future nonvolatile memory should be able to realize multi-level-cell(MLC) operation. The nano-floating gate nonvolatile memory device utilizing multilayer nanocrystals (NCs) has advantage that the charge storage density may be increased by increasing the layer of NCs. A MOS structure with double layer NiSi2 NCs was fabricated on p-type silicon wafers. NiSi2 (3nm) /Si3N4 (9nm) /NiSi2 (3nm) /SiO2 (30nm) layers were deposited onto 4nm-thick silicon oxide by sputtering. Then, rapid thermal annealing (RTA) process was performed in N2 ambient and at 800 °C for 180 sec to form NiSi2 NCs. The morphologies of the NiSi2 were characterized by SEM and TEM. Capacitance-voltage measurements show that the threshold voltage Vth shift depended on the value of sweep voltage, indicative of the variations in the charged electron density in the double layer NiSi2 NCs demonstrating MLC operation. The nonvolatile memory characteristic and the distribution in the Vth shift with variations on the interlay dielectric will also be discussed.