Fabrication of vertical nanochannel ZnO thin-film transistors

Abstract

Wide band gap semiconductors have been the subject of great interest for their potential application as active channel layers in transparent thin-film transistors (TFTs). Most ZnO TFT structures follow from existing device architectures consisting of a planar transport channel, bottom or top gate structure and symmetrical source-drain contacts [1]. We here introduce a vertical device structure that may reduce the source-drain distance of ZnO TFTs below 100 nm only using optical lithography. The lift-off edge of the bottom-gate acts as the template for the vertical ZnO channel. The angled deposition of contact metal results in the formation of a nanogap between the source and drain electrodes during deposition due to the shadowing effect of the vertical step-edge ZnO/oxide/gate structure (figure 1). This technique allows nanochannel TFTs to be fabricated without the need for high resolution lithography. The gate electrode was first defined by optical lithography, Ti (10 nm)/ W (150 nm) sputter deposition and lift-off. A 100 nm thick SiO2 gate insulation was sputtered for electrical isolation of the gate electrode. Then 200 nm think ZnO was sputtered at a rate of 2.3 nm/s. Rapid thermal annealing (RTA) of the ZnO was performed at 300 oC in 0.5 Torr N2 gas for 20 min to increase the crystallinity of the sputtered ZnO. The Ti/Au contacts were thermally evaporated at an angle of 60o to the sample surface and the shadowing effect of the gate electrode edge enabled the separation of the source-drain electrodes. It can be seen from figure 2 that the electrode separation was ~100 nm. We will present TFT transfer characteristics depending on device dimensions (channel length, component thin-film thicknesses) and ZnO preparation conditions (sputter deposition and RTA conditions).