Binarized Encoder-Decoder Network and Binarized Deconvolution Engine for Semantic Segmentation
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Hyunwoo | - |
dc.contributor.author | Kim, Jeonghoon | - |
dc.contributor.author | Choi, Jungwook | - |
dc.contributor.author | Lee, Jungkeol | - |
dc.contributor.author | Song, Yong Ho | - |
dc.date.accessioned | 2021-08-02T08:28:45Z | - |
dc.date.available | 2021-08-02T08:28:45Z | - |
dc.date.created | 2021-05-11 | - |
dc.date.issued | 2020-12 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/8184 | - |
dc.description.abstract | Recently, semantic segmentation based on deep neural network (DNN) has attracted attention as it exhibits high accuracy, and many studies have been conducted on this. However, DNN-based segmentation studies focused mainly on improving accuracy, thus greatly increasing the computational demand and memory footprint of the segmentation network. For this reason, the segmentation network requires a lot of hardware resources and power consumption, and it is difficult to be applied to an environment where they are limited, such as an embedded system. In this paper, we propose a binarized encoder-decoder network (BEDN) and a binarized deconvolution engine (BiDE) accelerating the network to realize low-power, real-time semantic segmentation. BiDE implements a binarized segmentation network with custom hardware, greatly reducing the hardware resource usage and greatly increasing the throughput of network implementation. The deconvolution used for upsampling in a segmentation network includes zero padding. In order to enable deconvolution in a binarized segmentation network that cannot express zero, we introduce zero-aware binarized deconvolution which skips padded zero activations and zero-aware batch normalization embedded binary activation considering zero-skipped convolution. The BEDN, which is a binarized segmentation network proposed to be accelerated on BiDE, has acceptable accuracy while greatly reducing the computational and memory demands of the segmentation network through full-binarization and simple structure. BEDN has a network size of 0.21 MB, and its maximum memory usage is 1.38 MB. BiDE was implemented on Xilinx ZU7EV field-programmable gate array (FPGA) to operate at 187.5 MHz. BiDE accelerated the proposed BEDN within CamVid11 images of 480 x 360 size at 25.89 frames per second (FPS) achieving a performance of 1.682 Tera operations per second (TOPS) and 824 Giga operations per second per watt (GOPS/W). | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Binarized Encoder-Decoder Network and Binarized Deconvolution Engine for Semantic Segmentation | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Choi, Jungwook | - |
dc.contributor.affiliatedAuthor | Song, Yong Ho | - |
dc.identifier.doi | 10.1109/ACCESS.2020.3048375 | - |
dc.identifier.scopusid | 2-s2.0-85099501848 | - |
dc.identifier.wosid | 000608193600001 | - |
dc.identifier.bibliographicCitation | IEEE ACCESS, v.9, pp.8006 - 8027 | - |
dc.relation.isPartOf | IEEE ACCESS | - |
dc.citation.title | IEEE ACCESS | - |
dc.citation.volume | 9 | - |
dc.citation.startPage | 8006 | - |
dc.citation.endPage | 8027 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | Y | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Telecommunications | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Telecommunications | - |
dc.subject.keywordPlus | Chemical activation | - |
dc.subject.keywordPlus | Decoding | - |
dc.subject.keywordPlus | Deep neural networks | - |
dc.subject.keywordPlus | Engines | - |
dc.subject.keywordPlus | Field programmable gate arrays (FPGA) | - |
dc.subject.keywordPlus | Low power electronics | - |
dc.subject.keywordPlus | Semantic Web | - |
dc.subject.keywordPlus | Semantics | - |
dc.subject.keywordPlus | Network coding | - |
dc.subject.keywordPlus | Computational demands | - |
dc.subject.keywordPlus | Custom hardwares | - |
dc.subject.keywordPlus | Frames per seconds | - |
dc.subject.keywordPlus | Giga-operations per seconds | - |
dc.subject.keywordPlus | Hardware resources | - |
dc.subject.keywordPlus | Real-time semantics | - |
dc.subject.keywordPlus | Semantic segmentation | - |
dc.subject.keywordPlus | Simple structures | - |
dc.subject.keywordAuthor | Deconvolution | - |
dc.subject.keywordAuthor | Image segmentation | - |
dc.subject.keywordAuthor | Hardware | - |
dc.subject.keywordAuthor | Semantics | - |
dc.subject.keywordAuthor | Memory management | - |
dc.subject.keywordAuthor | Acceleration | - |
dc.subject.keywordAuthor | Training | - |
dc.subject.keywordAuthor | Binarized neural network | - |
dc.subject.keywordAuthor | binarized deconvolution | - |
dc.subject.keywordAuthor | binarized segmentation network | - |
dc.subject.keywordAuthor | zero-aware deconvolution | - |
dc.subject.keywordAuthor | zero-skip deconvolution | - |
dc.subject.keywordAuthor | neural network accelerator | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9311614 | - |
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