Parasitic Inductance Reduction Design Method of Vertical Lattice Loop Structure for Stable Driving of GaN HEMT

Abstract

GaN HEMT is one of the most promising switching devices to be used. GaN HEMT has very low input capacitance enabling fast switching and very low conduction losses due to the 2DEG structure. However, the effect of parasitic inductance is prominent during fast switching, and the device's stability is degraded due to the small driving voltage range. The low threshold voltage can also cause the switch to turn on in unwanted situations. Therefore, the parasitic inductance should be reduced to stably drive sensitive GaN HEMT. Effects caused by parasitic inductance can be reduced through the circuit and physical value of parasitic inductance can also be reduced by design such as PCB. In this paper, a new method is used to reduce parasitic inductance, rather than reduce the influence of parasitic inductance through the circuit. Through this method, gate loop inductance and power loop inductance are reduced by more than 50% compared to the existing parasitic inductance reduction method. Using this method reduces ringing and overshoot caused by parasitic inductance, and reduces the rise and fall time of voltage and current. It also reduces switching on and off losses.