Hardware and Software Co-optimization for the Initialization Failure of the ReRAM-based Cross-bar Array
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Youngseok | - |
dc.contributor.author | Kim, Seyoung | - |
dc.contributor.author | Yeh, Chun-Chen | - |
dc.contributor.author | Narayanan, Vijay | - |
dc.contributor.author | Choi, Jungwook | - |
dc.date.accessioned | 2021-08-02T08:52:11Z | - |
dc.date.available | 2021-08-02T08:52:11Z | - |
dc.date.created | 2021-05-11 | - |
dc.date.issued | 2020-10 | - |
dc.identifier.issn | 1550-4832 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/8917 | - |
dc.description.abstract | Recent advances in deep neural network demand more than millions of parameters to handle and mandate the high-performance computing resources with improved efficiency. The cross-bar array architecture has been considered as one of the promising deep learning architectures that shows a significant computing gain over the conventional processors. To investigate the feasibility of the architecture, we examine non-idealities and their impact on the performance. Specifically, we study the impact of failed cells due to the initialization process of the resistive memory-based cross-bar array. Unlike the conventional memory array, individual memory elements cannot be rerouted and, thus, may have a critical impact on model accuracy. We categorize the possible failures and propose hardware implementation that minimizes catastrophic failures. Such hardware optimization bounds the possible logical value of the failed cells and allows us to compensate for the loss of accuracy via off-line training. By introducing the random weight defects during the training, we show that the model becomes more resilient on the device initialization failures, therefore, less prone to degrade the inference performance due to the failed devices. Our study sheds light on the hardware and software co-optimization procedure to cope with potentially catastrophic failures in the cross-bar array. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | ASSOC COMPUTING MACHINERY | - |
dc.title | Hardware and Software Co-optimization for the Initialization Failure of the ReRAM-based Cross-bar Array | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Choi, Jungwook | - |
dc.identifier.doi | 10.1145/3393669 | - |
dc.identifier.scopusid | 2-s2.0-85093701294 | - |
dc.identifier.wosid | 000577123300002 | - |
dc.identifier.bibliographicCitation | ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, v.16, no.4, pp.1 - 18 | - |
dc.relation.isPartOf | ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS | - |
dc.citation.title | ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS | - |
dc.citation.volume | 16 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 18 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.subject.keywordPlus | Deep learning | - |
dc.subject.keywordPlus | Deep neural networks | - |
dc.subject.keywordPlus | Network architecture | - |
dc.subject.keywordPlus | RRAM | - |
dc.subject.keywordPlus | Memory architecture | - |
dc.subject.keywordPlus | Array architecture | - |
dc.subject.keywordPlus | Catastrophic failures | - |
dc.subject.keywordPlus | Conventional memory | - |
dc.subject.keywordPlus | Hardware and software | - |
dc.subject.keywordPlus | Hardware implementations | - |
dc.subject.keywordPlus | Hardware optimization | - |
dc.subject.keywordPlus | High-performance computing resources | - |
dc.subject.keywordPlus | Learning architectures | - |
dc.subject.keywordAuthor | Inference | - |
dc.subject.keywordAuthor | accelerator | - |
dc.subject.keywordAuthor | neural networks | - |
dc.subject.keywordAuthor | ReRAM | - |
dc.identifier.url | https://dl.acm.org/doi/10.1145/3393669 | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
222, Wangsimni-ro, Seongdong-gu, Seoul, 04763, Korea+82-2-2220-1365
COPYRIGHT © 2021 HANYANG UNIVERSITY.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.