ScholarWorks@Hanyang University: Kwon, Daewoong

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Kwon, Daewoong (권대웅)

COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)

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Logic gates:13||FeFETs:8||Iron:7||Tunneling:5||Ferroelectric:5||Capacitors:4||/sub>:4||lowfrequency noise (LFN):4||Threshold voltage:4||hafnium zirconium oxide:4||Bandtoband tunneling (BTBT):4||sub>:4||Performance evaluation:3||ferroelectric tunnel junction:3||Voltage measurement:3||Transistors:3||Tin:3||ferroelectric:3||TFET:3||interface trap:2||Ferroelectric FET (FeFET):2||Electron traps:2||Bandtoband tunneling:2||TFETs:2||Capacitance:2||endurance characteristics of FeFET:2||memory:2||FeFET:2||vertically stacked nanosheet (NS):2||Ternary inverter:2||negative capacitance:2||negative capacitance FET:2||HZO:2||ferroelectric fieldeffect transistor (FeFET):2||Ferroelectric materials:2||ferroelectric memory:2||Junctions:2||pH Sensor:2||Hafnium zirconium oxide:2||Tunnel FET:2||Ferroelectric tunnel junction (FTJ):2||MOSFET:2||3D NAND flash memory:2||Market research:2||Zirconium:2||0.5<:2||Sputtered HZO:2||Ferroelectrics:2||Subthreshold swing (SS):2||Annealing:2||Switches:2||Ferroelectric tunnel junction:1||Ferroelectricgate FET (FeFET):1||Ferroelectricgate fieldeffect transistor (FeFET):1||Ferroelectricity annealing method:1||FieldEffect Transistor (FET) Based Biosensor:1||FinFETs:1||GIDLbased FET biosensor:1||Gateallaround (GAA) MOSFET:1||Gatenormal tunnel FET (TFET):1||Grain boundary trap:1||Grain size:1||Graphical models:1||Hafnium oxide:1||Hafnium oxide (HfOx):1||Hafnium zirconium oxide (HZO):1||Hf<:1||HfO2based ferroelectric memory:1||HfO2Highkappa:1||HfZrO2 ferroelectric (FE) material:1||HfxZr1xO2:1||Highκ spacer:1||Hump phenomenon:1||Hybrid sensing system of ISFET and CMOS readout circuits:1||Hysteresis:1||IGZO ferroelectric thinfilm transistors (FeTFT):1||ISFET:1||ISFET with CMOS circuit:1||Instability mechanism in alphaHIZO TFT:1||Integrated circuit modeling:1||IonSensitive FieldEffect Transistor (ISFET):1||Lshaped TFET:1||Layer selection by multilevel operation (LSM):1||Line tunneling:1||Linearity:1||Low power devices:1||Macro model of ISFET:1||Mathematical models:1||Metalferroelectricinsulatorsemiconductor:1||Microprocessors:1||Miller capacitance:1||MixedMode Device Simulation:1||Multilevel conductance:1||Multilevel conductance properties:1||Multiplexed biosensor:1||Negative capacitance:1||Neural networks:1||Neuromorphic systemsynaptic devicecapacitive neural network:1||Neurons:1||Nickel alloys:1||Nonvolatile Memory (NVM):1||O<:1||ONO Gate Stack:1||Onstate current:1||OneDirectional Current of TFET:1||Oxygen vacancy:1||PFM analysis:1||Parallel processing:1||Permittivity:1||Permittivity measurement:1||Phase transformation:1||Physical unclonable function:1||Physical unclonable function (PUF):1||Polarization coupling:1||PolySi:1||Processinginmemory (PIM):1||Pt bottom electrodes:1||Pt grain size:1||Ptnanoparticles:1||Pulse measurements:1||RRAM:1||Recessed channel:1||Reproducibility of results:1||Resistance:1||STDP:1||Scaling effects:1||Semiconductor device measurement:1||Semiconductor devices:1||Semiconductor process modeling:1||Silicidation:1||Silicides:1||Size measurement:1||Solid modeling:1||Spikeratedependent plasticity:1||Spiking neural networks (SNNs):1||Subthreshold swing:1||Subthresholdswing:1||Superlinear Onset of TFET:1||Switching Characteristic of TFET:1||Synaptic properties:1||TFET ternary CMOS (TCMOS):1||Temperature measurement:1||Ternary CMOS:1||Ternary CMOS (TCMOS):1||Threshold switching:1||Threshold voltagetunable CMOS readout circuits:1||Thyristor:1||TiO<:1||Training:1||Transient drain current:1||Transparent RRAM:1||Tunnel FET biosensor:1||Tunnel FieldEffect Transistor (TFET):1||Ultrathin:1||Ultrathin ferroelectric:1||Vertical tunnel fieldeffect transistor (vertical tunnel FET):1||Virtual machine monitors:1||Voltage:1||Zr<:1||ac conductance:1||artificial intelligence:1||asymmetric pass voltage:1||bandtoband tunneling:1||bandtoband tunneling (BTBT):1||binary neural network (BNN):1||capacitance matching:1||channel length, 1/f noise:1||content addressable memory:1||corner BTBT:1||deep learning:1||doublegate FeTFT:1||ferroelectric (FE) material:1||ferroelectric FET:1||ferroelectric FET (FeFET):1||ferroelectric FETs:1||ferroelectric hafnium oxide (HfO (x) )interlayer engineering:1||ferroelectric junctionless thinfilm transistor (FE JL TFT):1||ferroelectric recessed channel:1||ferroelectric tunnel junction (FTJ):1||ferroelectric tunnel junctions:1||ferroelectric variation:1||ferroelectricgate FET (FeFET):1||ferroelectricgate fieldeffect transistor (FeFET):1||ferroelectricgate fieldeffecttransistor (FeFET):1||ferroelectricity:1||forksheet device:1||frequency multiplier:1||fully depleted silicononinsulator (FDSOI):1||gate last:1||gate work function (WF):1||gateallaround (GAA) fieldeffect transistor (GAAFET):1||gatefirst process:1||gatenormal tunnel FET:1||grain size engineering:1||ground plane (GP) doping:1||hafnium oxide:1||hafnium oxide (HfO2):1||highk dielectrics:1||highpressure annealing:1||highpressure annealing (HPA):1||inmemorycomputing:1||insulator:1||interface traps:1||interlayer:1||laminated metal:1||landaukhalatnikov (LK) model:1||length:1||line tunneling:1||localboosting scheme:1||logicinmemory:1||multiinput processing SNN system:1||multivalued logic:1||nearthresholdvoltage (NTV) design:1||negative capacitance (NC):1||negative capacitance field effect transistor:1||negative capacitance fieldeffect transistor (NCFET):1||negative differential resistance:1||negative drain induced barrier lowering (DIBL):1||neuromorphic computing:1||neuromorphic training method:1||offchip learning:1||physical unclonable functions:1||polarization:1||polarization enhancement:1||polarization switching speed:1||program disturbance:1||random spatial distribution:1||read disturbance by negative boosting (NB):1||read disturbance in 3D NAND flash memory:1||recess channel:1||resistive switching memory:1||reverse DIBL:1||reverse drain induced barrier lowering:1||scaling:1||selective detection:1||selfaligned nickelsilicide (NiSi):1||semiconductor structure:1||series resistance:1||shafnium zirconium oxide:1||short channel effects:1||shortchannel effects:1||shortchannel transistor:1||silicononinsulator:1||sputtering damage:1||stacked nanosheet (NS):1||subthreshold swing:1||subthreshold swing (SS):1||technology computeraided design (TCAD):1||temperature effects on electrical properties in alphaHIZO TFT:1||ternarycomplementary metaloxidesemiconductor (TCMOS):1||tungsten oxide:1||tunnel FETs (TFET):1||tunnel fieldeffect transistor (TFET):1||ultrathin ferroelectricity:1||variability:1||vectormatrix multiplication (VMM):1||vertical TFET:1||vertical structure:1||wakeup:1||work function fluctuation:1||:1||x<:1||1/f noise:1||1TDRAM:1||2<:1||3D nand architecture:1||3D NAND:1||3D stacked NAND flash memory:1||AC switching characteristics of TFET:1||ALD:1||ALD TaNnanoparticles:1||Ambipolar current:1||Biological neural networks:1||Biosensor with CMOS readout circuit:1||Body thickness:1||Boolean logics:1||CSA:1||CapacitorLess DRAM:1||Channel stacked NAND flash memory:1||Chemical solution deposition:1||Circuit model of ISFET:1||Cointegration of ISFETs and CMOS devices:1||Computational modeling:1||Computer architecture:1||Corner tunneling:1||Creep:1||Cryptographic primitive:1||Cryptography:1||Damagefree sensing oxide in ISFET:1||Defectinduced polarization switching:1||DepressionTransistors:1||Device design margin:1||Dopant activation:1||Doping:1||Drift effect mechanism:1||Drift effect modeling:1||DualGate:1||Electrodes:1||Endurance:1||FTJ crossbar arrays:1||FeFET endurance:1||FeFET program/erase speed:1||FeFET synaptic device:1||FeFETsTraining:1||FeTFT:1||Ferroelectric (FE):1||Ferroelectric Memory:1||Ferroelectric devices:1||Ferroelectric devicesone transistor dynamic randomaccess memory (1TDRAM):1||Ferroelectric fieldeffect transistor (FeFET) with dual metal gates:1||Ferroelectric hafnium oxide (HfOx):1||Ferroelectric memory:1||

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222, Wangsimni-ro, Seongdong-gu, Seoul, 04763, Korea+82-2-2220-1365

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