ScholarWorks@Hanyang University: Chung, Ki Seok

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Chung, Ki Seok (정기석)

COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)

Research Area: Embedded Systems, SoC Design

Tel 02-2220-0396
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LDPC decoder:9||DRAM:7||parallel processing:6||OpenCL:5||decoder:5||LDPC:5||DRAM chips:4||CUDA:4||SNR estimation:4||SoC:4||Multicore:4||Low power:4||Parallel processing:3||reconfigurable system:3||Low Power Design:3||FPGA:3||Heterogeneous computing:3||embedded system:3||Dynamic Power Management:3||H.264/AVC:3||Reliability:3||CMMB:3||ARM:3||Load balancing:3||Embedded OS:3||SDSoC:3||Error correcting code:3||Modified UMPBP:2||simulation:2||Decoder:2||Decoding:2||spatiotemporal:2||Multicore:2||low power:2||Quantization:2||Embedded System:2||Barrel Shifter:2||lowpower design:2||main memory:2||RowHammer:2||NUMA:2||video object detection:2||virtual platform:2||memory controller:2||Neural networks:2||Low Power:2||convolutional neural network (CNN):2||저전력:2||minsum algorithm:2||Semisupervised learning:2||Noisy data:2||Hamming distance:2||Component:2||Object detection:2||CNN:2||Adversarial Attack:2||dynamic random access memory:2||neural processing unit (NPU):2||MAC:2||MDCT/IMDCT:2||Temperature prediction:2||CPU:2||MP3:2||ACM:2||DSP:2||power consumption:2||Fault Tolerance:2||Ubiquitous:2||Parallel:2||Feature extraction:2||IMDCT:2||DVFS:2||huffman:2||Dynamic Thermal Management:2||infotainment:2||GPGPU:2||Adaptive modified UMPBP:2||Gpgpu:1||Graphic Processing Unit:1||Graphics processors:1||H.264:1||HEVC:1||HEVC decoder:1||HLS:1||HW/SW CoDesign:1||Hard decision:1||Hardware Accelerator:1||Hardware Optimization:1||Hardware Security:1||Heterogenous system:1||High level synthesis:1||Highlevel synthesis:1||Hot data detection:1||Hybrid architecture:1||IDCT IP:1||Identification:1||Image blending:1||Image filter:1||Image pyramid:1||Image restoration:1||InDRAM ECC:1||Iterative decoding:1||Iterative hardreliabilitybased majoritylogic decoding algorithm:1||LLMs:1||LeNet5:1||League of Legends:1||Lenet5:1||Level shifter:1||Low Density Parity Check (LDPC) codes:1||Low density parity check:1||Low power DRAM:1||LowPower Design:1||Lowcomplexity decoding:1||Lowdensity paritycheck code:1||Lowdensity paritycheck codes:1||MOBA game:1||MPEG4 AVC:1||Machine learning:1||Manycore:1||Memory System:1||Memory architecture:1||Memory control and access:1||Memory management:1||Memory structures:1||Message truncation rule:1||Micromechanical devices:1||Microprocessor:1||Minsum algorithm:1||Mobile device:1||Model compresion:1||MultiVdd:1||Multiband blending:1||Multicore CPU:1||Multirate support:1||Multiresolution spline:1||Multiplier:1||Mutual dependency.:1||NAND flash:1||NAND flash memory:1||NLP:1||NearMemory Processing:1||Noise:1||Noisy Label:1||Noisy label:1||NonBinary Low Density Parity Check codes:1||Nonbinary Lowdensity Parity Check:1||Nonbinary lowdensity paritycheck codes:1||Normalized minsum algorithm:1||Ocr:1||Ondevice learning:1||OpenCL Framework:1||OpenMP:1||Operating System:1||Optical flow estimation:1||OutofDistribution Detection:1||Output stationary:1||Overlapped Message Passing:1||PRAM:1||Padding:1||Parallel Processing:1||Partially parallel decoder:1||Performance:1||Physical unclonable function:1||Power:1||Power Management Unit:1||Power consumption:1||Power gating:1||Power management:1||Power management test:1||Prediction:1||Prediction algorithms:1||Probabilistic Method:1||Process management:1||Process variation:1||Proposals:1||Pruning:1||RICAP:1||Refrseh:1||Reinforcement Learning:1||RetentionAware Refresh:1||RunBefore decoder:1||SDR:1||SIMD:1||SW architecture:1||Scheduler:1||Security:1||SelfSupervision:1||Shared memory:1||Side channel attack (SCA):1||Softmax:1||Software parallelization:1||Sparse MatrixVector Multiplication:1||Spatiotemporal phenomena:1||State retention:1||System on chip:1||Systolic array:1||Task analysis:1||Temperature:1||Tensor ordering:1||Termination of employment:1||Thermal management:1||Thermal sensor:1||Transformer:1||Transformer cores:1||Transformer models:1||Unbalanced Dataset:1||Uncertainty:1||Unified kernel:1||VLSI:1||Variable Precision:1||Verification:1||Video object detection:1||Video recording:1||Weight Pruning:1||Winning Probability:1||Winograd convolution algorithm:1||access latency improvement:1||activate operations:1||active links:1||adaptive minsum algorithm:1||adaptive minsum decoding:1||address bus width:1||adiabatic logic:1||aggressor row:1||applicationspecific traffic:1||autoactivate operation:1||autorefresh operation:1||autonomous highspeed serial link power management:1||buffer storage:1||capacitor:1||charge leakage:1||circuit size:1||clock synchronisation:1||coverification:1||computer vision:1||constant multiplication:1||conventional DRAM:1||convolutional neural network:1||coreset:1||data augmentation:1||data loss:1||decoding:1||deep learning:1||differential power analysis (DPA):1||diffusion model:1||digital arithmetic:1||digital signal processors:1||diversityaware:1||dpm:1||dynamic RAM:1||early termination refresh:1||energyaware system:1||energyaware systems:1||ensemble:1||error correction codes:1||etc.:1||explicit activate command:1||extra address bus pins:1||frame partitioning:1||graphic processing unit:1||hardware/software interfaces:1||heterogeneous computing:1||heterogeneous multicore system:1||high density DRAM:1||high performance DRAM architecture:1||highdensity DRAM devices:1||highspeed DRAM interface:1||highspeed link:1||hybrid memory cube:1||image patch:1||interconnection:1||interpolation:1||label smoothing:1||latency penalty:1||leakage power:1||learning with noisy label:1||levelup shifter:1||link performance:1||link power consumption reduction:1||long mode transition times:1||low area (152):1||low power consumption:1||lowdensity parity check (LDPC) code:1||lowdensity paritycheck codes:1||lowpower HMCbased system:1||lowpower LDPC decoder:1||lowpower modes:1||matrix multiplication:1||memory architecture:1||memory array:1||memory bus:1||memory design:1||memory profiler:1||memory scheduling:1||memory used as logic:1||memoryintensive applications:1||min sum algorithm:1||mobile systems:1||model compression:1||modeling of computer architecture:1||motion compensation:1||multiVDD:1||multicore:1||multicore systems:1||multicore:1||multicore systems:1||multicycle row addressing:1||multiple cycles:1||multiple data stream srchitectures:1||multiprocessing systems:1||neural network accelerator:1||neural networks:1||novel row:1||open multiprocessing (OpenMP):1||optimal placement:1||parallel entropy decoding:1||performance evaluation:1||performance metrics:1||power analysis:1||power aware computing:1||power consumption increase:1||power gating:1||precharge command:1||precharge operations:1||probabilitybased:1||read commands:1||refresh:1||refresh overhead reduction:1||regularization:1||reliability:1||row addressing scheme:1||rowhammering:1||runtime analysis:1||scheduling:1||security:1||semisupervised learning:1||significant performance degradation:1||singlecycle row:1||sparsityaware acceleration:1||split row buffer:1||storage management:1||switching capacitance:1||synchronisation:1||system buses:1||system on chip design:1||system performance:1||system performance degradation:1||target row address:1||temperature:1||threedimensional integrated circuits:1||traffic generator:1||transistor:1||unatecovering problem:1||unused address bus:1||various shapes and dimensions:1||victim row:1||video decoder:1||weakest memory cell:1||write commands:1||동적전력관리:1||멀티코어:1||멀티코어:1||재구성 가능한 DSP:1||전력:1||전력관리정책:1||3Dstacked DRAMs:1||커널:1||3Dstacked dynamic RAMs:1||802.11a:1||AI:1||AI accelerator:1||AMBA:1||APU:1||ASIP:1||Action Recognition:1||Adversarial Training:1||AlgorithmHardware CoDesign:1||Algorithms:1||Attention mechanism:1||Audio coding:1||Audio decoder:1||Authentication:1||Bebavior pattern analysis:1||Behavior pattern analysis:1||CABAC:1||CAVLC decoder:1||CAVLC decoding:1||CNN inference:1||CPU frequency scaling:1||Classification:1||Clock gating:1||Cloud:1||Complexity theory:1||Compute cycles:1||Condition monitoring:1||Conditioning:1||ConfidenceCalibration:1||Convolution neural network:1||Convolutional Neural Network:1||Curriculum Learning:1||DFS:1||DPM:1||DRAM density increases:1||DRAM device:1||DRAM devices:1||DRAM memory cells:1||DRAM refresh:1||DTM:1||Data transfer:1||Dataflow, Weight stationary:1||Deep Learning:1||Deep Neural Network:1||Deep learning:1||Depthwise convolution:1||Design:1||Detectors:1||Differential amplifier:1||Diverse branch:1||Domain Adaptation:1||Driver Status Monitoring:1||DualVdd:1||Dynamic Partitioning:1||Dynamic power management:1||EMA:1||ETR:1||Edge device:1||Embedded multicore system:1||Embedded system design:1||Energy monitoring:1||Error analysis:1||Error correction codes:1||Errorcorrection code:1||Esports:1||Extended MinSum algorithm:1||Extended Minsum Algorithm:1||FOD:1||Field programmable gate array:1||Filter Pruning:1||First one detector:1||Functional Unit Sharing:1||GMAC:1||GPP:1||GPU:1||

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