Cross-layer resilience in low-voltage digital systems: Key insights
DC Field | Value | Language |
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dc.contributor.author | Cheng | - |
dc.contributor.author | E. | - |
dc.contributor.author | Abraham | - |
dc.contributor.author | J. | - |
dc.contributor.author | Bose | - |
dc.contributor.author | P. | - |
dc.contributor.author | Buyuktosunoglu | - |
dc.contributor.author | A. | - |
dc.contributor.author | Campbell | - |
dc.contributor.author | K. | - |
dc.contributor.author | Chen | - |
dc.contributor.author | D. | - |
dc.contributor.author | Cher | - |
dc.contributor.author | C.-Y. | - |
dc.contributor.author | Cho, Hyungmin | - |
dc.contributor.author | H. | - |
dc.contributor.author | Le | - |
dc.contributor.author | B. | - |
dc.contributor.author | Lilja | - |
dc.contributor.author | K. | - |
dc.contributor.author | Mirkhani | - |
dc.contributor.author | S. | - |
dc.contributor.author | Skadron | - |
dc.contributor.author | K. | - |
dc.contributor.author | Stan | - |
dc.contributor.author | M. | - |
dc.contributor.author | Szafaryn | - |
dc.contributor.author | L. | - |
dc.contributor.author | Vezyrtzis | - |
dc.contributor.author | C. | - |
dc.contributor.author | Mitra | - |
dc.contributor.author | S. | - |
dc.date.available | 2021-03-17T09:42:39Z | - |
dc.date.created | 2021-02-26 | - |
dc.date.issued | 2017 | - |
dc.identifier.issn | 1063-6404 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/13302 | - |
dc.description.abstract | CLEAR (Cross-Layer Exploration for Architecting Resilience) is a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to hardware errors: achieve desired resilience targets at low cost (energy, power, execution time, area) by combining resilience techniques across various layers of the system stack (circuit, logic, architecture, software, algorithm). CLEAR automatically and systematically explores the large space of resilience techniques and their combinations, derives cost-effective solutions, provides guidelines for designing new techniques, and offers insights into how to design cost-effective digital systems resilient to hardware errors: 1. circuit-level techniques are crucial; 2. application-level guidance is essential; 3. existing architecture and software techniques are generally expensive or provide too little resilience; 4. some previously published techniques suffer from inaccurate analysis, leading to incorrect conclusions; 5. cost-effective protection from multiple error sources is achieved by combining techniques targeting each specific error source. | - |
dc.publisher | IEEE | - |
dc.title | Cross-layer resilience in low-voltage digital systems: Key insights | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Cho, Hyungmin | - |
dc.identifier.doi | 10.1109/ICCD.2017.103 | - |
dc.identifier.scopusid | 2-s2.0-85041651215 | - |
dc.identifier.wosid | 000424789300093 | - |
dc.identifier.bibliographicCitation | Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017, pp.593 - 596 | - |
dc.relation.isPartOf | Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017 | - |
dc.citation.title | Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017 | - |
dc.citation.startPage | 593 | - |
dc.citation.endPage | 596 | - |
dc.type.rims | ART | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | cross-layer resilience | - |
dc.subject.keywordAuthor | soft errors | - |
dc.subject.keywordAuthor | voltage noise | - |
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