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SiNx / 고분자 이중층 게이트 유전체를 가진 Zinc 산화물 박막 트랜지스터의 저온 SiNx / 고분자 이중층 게이트 유전체를 가진 Zinc 산화물 박막 트랜지스터의 저온 공정에 관한 연구

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dc.contributor.author이호원-
dc.contributor.author양진우-
dc.contributor.author형건우-
dc.contributor.author박재훈-
dc.contributor.author구자룡-
dc.contributor.author조의식-
dc.contributor.author권상직-
dc.contributor.author김우영-
dc.contributor.author김영관-
dc.date.accessioned2021-12-17T03:42:02Z-
dc.date.available2021-12-17T03:42:02Z-
dc.date.created2021-12-16-
dc.date.issued2010-
dc.identifier.issn1225-9098-
dc.identifier.urihttps://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/21334-
dc.description.abstractOxide semiconductors Thin-film transistors are an exemplified one owing to its excellent ambient stability and optical transparency. In particular zinc oxide (ZnO) has been reported because It has stability in air, a high electron mobility, transparency and low light sensitivity, compared to any other materials. For this reasons, ZnO TFTs have been studied actively. Furthermore, we expected that would be satisfy the demands of flexible display in new generation. In order to do that, ZnO TFTs must be fabricated that flexible substrate can sustain operating temperature. So, In this paper we have studied low-temperature process of zinc oxide(ZnO) thin-film transistors(TFTs) based on silicon nitride (SiNx ) /cross-linked poly-vinylphenol (C-PVP) as gate dielectric. TFTs based on oxide fabricated by Low-temperature process were similar to electrical characteristics in comparison to conventional TFTs. These results were in comparison to device with SiNx / low-temperature C-PVP or SiNx / conventional C-PVP. The ZnO TFTs fabricated by low-temperature process exhibited a field-effect mobility of 0.205 cm2/Vs, a thresholdvoltage of 13.56 V and an on/off ratio of 5.73 x 106. As a result, We applied experimental for flexible PET substrate and showed that can be used to ZnO TFTs for flexible application.-
dc.language한국어-
dc.language.isoko-
dc.publisher한국응용과학기술학회-
dc.titleSiNx / 고분자 이중층 게이트 유전체를 가진 Zinc 산화물 박막 트랜지스터의 저온 SiNx / 고분자 이중층 게이트 유전체를 가진 Zinc 산화물 박막 트랜지스터의 저온 공정에 관한 연구-
dc.typeArticle-
dc.contributor.affiliatedAuthor김영관-
dc.identifier.bibliographicCitation한국응용과학기술학회지, v.27, no.2, pp.137 - 143-
dc.relation.isPartOf한국응용과학기술학회지-
dc.citation.title한국응용과학기술학회지-
dc.citation.volume27-
dc.citation.number2-
dc.citation.startPage137-
dc.citation.endPage143-
dc.type.rimsART-
dc.identifier.kciidART001462484-
dc.description.journalClass2-
dc.description.journalRegisteredClasskci-
dc.subject.keywordAuthorZnO transistor-
dc.subject.keywordAuthorLow temperature process-
dc.subject.keywordAuthorC-PVP-
dc.subject.keywordAuthorFlexible substrate-
dc.subject.keywordAuthorALD-
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