Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package
DC Field | Value | Language |
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dc.contributor.author | Jee, Y. K. | - |
dc.contributor.author | Yu, J. | - |
dc.contributor.author | Park, K. W. | - |
dc.contributor.author | Oh, T. S. | - |
dc.date.accessioned | 2022-01-03T05:43:22Z | - |
dc.date.available | 2022-01-03T05:43:22Z | - |
dc.date.created | 2021-12-28 | - |
dc.date.issued | 2009-05 | - |
dc.identifier.issn | 0361-5235 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/21865 | - |
dc.description.abstract | Microvias of 50 mu m diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed to fill the via holes with the electroplated Zn. In the case of the dipping method, Zn via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa during the via-filling is essential for ensuring that the via holes are completely filled with Zn or Sn-Zn and for preventing voids from being trapped in the vias. The melting temperature and electrical conductivity of the Sn-Zn alloys increases almost linearly with the content of Zn, implying that the thermal and electrical properties of the Sn-Zn vias can be easily controlled by varying the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by flip-chip bonding of three chips with Zn vias. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | SPRINGER | - |
dc.title | Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Oh, T. S. | - |
dc.identifier.doi | 10.1007/s11664-008-0646-6 | - |
dc.identifier.scopusid | 2-s2.0-62549132454 | - |
dc.identifier.wosid | 000264176300009 | - |
dc.identifier.bibliographicCitation | JOURNAL OF ELECTRONIC MATERIALS, v.38, no.5, pp.685 - 690 | - |
dc.relation.isPartOf | JOURNAL OF ELECTRONIC MATERIALS | - |
dc.citation.title | JOURNAL OF ELECTRONIC MATERIALS | - |
dc.citation.volume | 38 | - |
dc.citation.number | 5 | - |
dc.citation.startPage | 685 | - |
dc.citation.endPage | 690 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordAuthor | Chip-stack package | - |
dc.subject.keywordAuthor | system-in-package | - |
dc.subject.keywordAuthor | through-silicon via | - |
dc.subject.keywordAuthor | Zn via | - |
dc.subject.keywordAuthor | Sn-Zn via | - |
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