저전력 응용을 위한 28 nm 금속 게이트/high-k MOSFET 디자인

Abstract

This paper explores 28 nm MOSFET design for LSTP (Low Standby Power) applications using TCAD (Technology Computer Aided Design) simulation. Simulated results show that the leakage current of the MOSFET is increasingly dominated by GIDL (Gate Induced Drain Leakage) instead of a subthreshold leakage as the Source/Drain extension doping increases. The GIDL current can be reduced by grading lateral abruptness of the drain at the expense of a higher Source/Drain series resistance. For 28 nm MOSFET suggested in ITRS, we have shown Source/Drain design becomes even more critical to meet both leakage current and performance requirement.