Synthesis and optimization of combinational interface circuits
DC Field | Value | Language |
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dc.contributor.author | Chung, KS | - |
dc.contributor.author | Gupta, RK | - |
dc.contributor.author | Kim, T | - |
dc.contributor.author | Liu, CL | - |
dc.date.accessioned | 2022-04-11T02:42:13Z | - |
dc.date.available | 2022-04-11T02:42:13Z | - |
dc.date.created | 2022-04-11 | - |
dc.date.issued | 2002-07 | - |
dc.identifier.issn | 0922-5773 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/26817 | - |
dc.description.abstract | We describe an algorithm for interface synthesis and optimization for embedded system components such as microprocessors, memory ASIC, and network subsystems. The algorithm accepts the timing characteristics of two chips as input, and generates a combinational interface circuitry to implement communication between them. The algorithm consists of two parts. In the first part, we determine the direct pin-to-pin connections employing a 0-1 ILP formulation to minimize wiring area and dynamic power consumption in the resulting interface circuit. In the second part, we use a novel encoding method to synthesize connections between chips which require additional gates in the interface circuit. Experiments show that our algorithm is very effective in practice. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | KLUWER ACADEMIC PUBL | - |
dc.subject | GENERATION | - |
dc.title | Synthesis and optimization of combinational interface circuits | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Chung, KS | - |
dc.identifier.doi | 10.1023/A:1015413306258 | - |
dc.identifier.scopusid | 2-s2.0-0036644369 | - |
dc.identifier.wosid | 000175569000004 | - |
dc.identifier.bibliographicCitation | JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, v.31, no.3, pp.243 - 261 | - |
dc.relation.isPartOf | JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | - |
dc.citation.title | JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | - |
dc.citation.volume | 31 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 243 | - |
dc.citation.endPage | 261 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | GENERATION | - |
dc.subject.keywordAuthor | interface synthesis | - |
dc.subject.keywordAuthor | logic circuit | - |
dc.subject.keywordAuthor | embedded systems | - |
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