Characteristics of the MFIS-FET structures processed using SBT ferroelectric thin films

Abstract

Pt/SBT/TiO(2)/Si and Pt/SBT/ZrO(2)/Si structures were prepared for the metal/ferroelectric/insulator/semiconductor field effect transistor (MFIS-FET) applications. After depositing TiO(2) or ZrO(2) film of 10-50 nm. thickness by reactive sputtering on Si(100) substrate as buffer layer, SBT thin film of 400 nm thickness was prepared onto it using liquid source misted chemical deposition. Maximum capacitance of the Pt/SBT/TiO(2)/Si and Pt/SBT/ZrO(2)/Si structures increased with decreasing the thickness of TiO(2) and ZrO(2) buffer layers. Pt/SBT/TiO(2)/Si and Pt/SBT/ZrO(2)/Si structures exhibited well-defined C-V hysteresis loop. Memory windows of the Pt/SBT(400 nm)/TiO(2)(10 nm)/Si and Pt/SBT(400 nm)/ZrO(2)(10 nm)/Si were 1.6 V and 0.72 V at 5 V, respectively.