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Minimizing Total Wire Length by Flipping Modules
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Chong, K. | - |
| dc.contributor.author | Sahni, S. | - |
| dc.date.accessioned | 2022-05-24T02:48:38Z | - |
| dc.date.available | 2022-05-24T02:48:38Z | - |
| dc.date.created | 2022-05-24 | - |
| dc.date.issued | 1993 | - |
| dc.identifier.issn | 0278-0070 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/28078 | - |
| dc.description.abstract | We consider the problem of flipping modules about their horizontal and/or vertical axes so as to minimize the estimated total wire length. Polynomial time algorithms are proposed for some classes of module layouts. Further, it is shown that a simple greedy heuristic often outperforms the neural network and simulated annealing heuristics proposed earlier for this problem. © 1993 IEEE | - |
| dc.language | 영어 | - |
| dc.language.iso | en | - |
| dc.title | Minimizing Total Wire Length by Flipping Modules | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Chong, K. | - |
| dc.identifier.doi | 10.1109/43.184854 | - |
| dc.identifier.scopusid | 2-s2.0-33751424535 | - |
| dc.identifier.bibliographicCitation | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.12, no.1, pp.167 - 175 | - |
| dc.relation.isPartOf | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | - |
| dc.citation.title | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | - |
| dc.citation.volume | 12 | - |
| dc.citation.number | 1 | - |
| dc.citation.startPage | 167 | - |
| dc.citation.endPage | 175 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Article | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalRegisteredClass | scopus | - |
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