Energy Reduction in Asymmetric Write Operations of STT-MRAMs

Abstract

In STT-MRAMs, switching characteristics of MTJ and the source degeneration of the access transistor lead to unbalanced switching times for P-to-AP and AP-to-P (P: parallel, AP: anti-parallel) transitions during write operations: one transition (AP-to-P) completes faster than the other transition (P-to-AP). As a result, the bit-cell write time is determined by the P-to-AP switching. However, for bit-cells undergoing AP-to-P transition, the current flows through the bit-cells even after the switching is complete, leading to unnecessary write energy consumption. In order to address the write energy wastage and improve energy efficiency of an STT-MRAM, we propose three design techniques: 1) Low-voltage Bit-Line Drive (LBLD), 2) Bit-Line Gating (BLG), and 3) Hybrid Bit-Line Driver (HBLD). The proposed techniques achieve write energy reduction by 71-84% for AP-to-P switching.