A 10-Gbps Receiver Bridge Chip with Deserializer for FPGA-based Frame Grabber Supporting MIPI CSI-2
DC Field | Value | Language |
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dc.contributor.author | Lee, Pil-Ho | - |
dc.contributor.author | Lee, Han-Yeol | - |
dc.contributor.author | Kim, Yeong-Woong | - |
dc.contributor.author | Hong, Han-Young | - |
dc.contributor.author | Jang, Young-Chan | - |
dc.date.available | 2020-04-24T11:25:14Z | - |
dc.date.created | 2020-03-31 | - |
dc.date.issued | 2017-08 | - |
dc.identifier.issn | 0098-3063 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/1070 | - |
dc.description.abstract | A 2.5-Gbps/lane receiver bridge chip, which fully supports the protocol of the D-PHY version 1.2 for the mobile industry processor interface (MIPI) camera serial interface (CSI)-2, is proposed for a field-programmable gate array (FPGA)-based frame grabber. The proposed receiver bridge chip converts four-lane high-speed data of scalable low-voltage signaling (SLVS) of the MIPI CSI-2 into 32 low-speed data of low-voltage CMOS (LVCMOS) signaling for a parallel interface with a FPGA chip. In order to achieve this, each data lane of the proposed receiver bridge chip has a 1-to-8 deserializer including a byte synchronizer. Furthermore, an asynchronous delay line per lane compensates the time skew among the five lanes, including a clock lane. A common-gate level shifter (CGLS) with a continuous-time linear equalizer (CTLE) is proposed to improve the voltage gain and bandwidth of the high-speed receiver. The proposed receiver bridge chip is implemented using a 0.11-mu m CMOS process with a 1.2 V supply. The area and power consumption of the proposed receiver bridge chip are 5.29 mm(2) and 7.2 mW/Gbps/lane, respectively. The proposed CTLE of the high-speed receiver achieves the improved peak-to-peak time jitter of 0.3UI at a data rate of 3.0 Gbps/lane. The FPGA-based frame grabber processes the image or video data supplied by a camera sensor with the MIPI CSI-2 by using the proposed receiver bridge chip. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | NM CMOS | - |
dc.title | A 10-Gbps Receiver Bridge Chip with Deserializer for FPGA-based Frame Grabber Supporting MIPI CSI-2 | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Jang, Young-Chan | - |
dc.identifier.doi | 10.1109/TCE.2017.014908 | - |
dc.identifier.scopusid | 2-s2.0-85036457196 | - |
dc.identifier.wosid | 000415115900001 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, v.63, no.3, pp.209 - 215 | - |
dc.citation.title | IEEE TRANSACTIONS ON CONSUMER ELECTRONICS | - |
dc.citation.volume | 63 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 209 | - |
dc.citation.endPage | 215 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.subject.keywordPlus | NM CMOS | - |
dc.subject.keywordAuthor | Mobile industry processor interface (MIPI) | - |
dc.subject.keywordAuthor | camera serial interface (CSI)-2 | - |
dc.subject.keywordAuthor | frame grabber | - |
dc.subject.keywordAuthor | receiver bridge chip | - |
dc.subject.keywordAuthor | continuous-time linear equalizer | - |
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