An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock
DC Field | Value | Language |
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dc.contributor.author | Lee, Pil-Ho | - |
dc.contributor.author | Lee, Han-Yeol | - |
dc.contributor.author | Lee, Hyun-Bae | - |
dc.contributor.author | Jang, Young-Chan | - |
dc.date.available | 2020-04-24T11:25:17Z | - |
dc.date.created | 2020-03-31 | - |
dc.date.issued | 2017-04 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/1087 | - |
dc.description.abstract | This paper presents an on-chip monitoring circuit (OCMC) for analyzing the signal integrity of highspeed signals for a chip-to-chip interface with a source-synchronous clocking scheme. The proposed OCMC consists of a fractional-N phase-locked loop (PLL)-based frequency synthesizer, a high-bandwidth track-and-hold circuit, and a 10-bit analog-to-digital converter (ADC) to implement a subsampling scheme. The proposed fractional-N PLL-based frequency synthesizer improves the time jitter accumulated in a voltage-controlled oscillator using a fractional frequency divider operated by an eight-phase clock. The bandwidth of the track-and-hold circuit is designed to be 6 GHz, using inductive peaking realized through a source follower. The OCMC samples 49 points over two unit intervals of a high-speed input signal when the frequency multiplication of the frequency synthesizer is 6.125/6. The 10-bit ADC uses the architecture of a pipelined successive approximation register ADC to reduce the power consumption and chip area. The proposed OCMC is implemented with 65-nm CMOS technology and a 1.2 V supply. The 8-Gb/s chip-to-chip interface signal is reconstructed with time and voltage resolutions of 5.1 ps and 1.17 mV, respectively. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | WAVE-FORMS | - |
dc.subject | JITTER | - |
dc.subject | OSCILLOSCOPE | - |
dc.title | An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Jang, Young-Chan | - |
dc.identifier.doi | 10.1109/TVLSI.2016.2639289 | - |
dc.identifier.scopusid | 2-s2.0-85008440916 | - |
dc.identifier.wosid | 000398858800018 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.4, pp.1386 - 1396 | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 25 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 1386 | - |
dc.citation.endPage | 1396 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.subject.keywordPlus | WAVE-FORMS | - |
dc.subject.keywordPlus | JITTER | - |
dc.subject.keywordPlus | OSCILLOSCOPE | - |
dc.subject.keywordAuthor | Chip-to-Chip interface | - |
dc.subject.keywordAuthor | fractional divider | - |
dc.subject.keywordAuthor | fractional-N phase-locked loop (PLL) | - |
dc.subject.keywordAuthor | frequency synthesizer | - |
dc.subject.keywordAuthor | inductive peaking | - |
dc.subject.keywordAuthor | on-chip monitoring circuit (OCMC) | - |
dc.subject.keywordAuthor | subsampling | - |
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