A 10-bit 100-MS/s Pipelined SAR ADC with Redundancy Generation using Capacitor-based DAC and Linearity-improved Dynamic Amplifier
- Authors
- Lee, Han-Yeol; Youn, Eunji; Jang, Young-Chan
- Issue Date
- Aug-2019
- Publisher
- IEEK PUBLICATION CENTER
- Keywords
- Pipelined SAR ADC; redundancy generation; dynamic amplifier; input range calibration; digital error correction
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.19, no.4, pp.378 - 387
- Journal Title
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- Volume
- 19
- Number
- 4
- Start Page
- 378
- End Page
- 387
- URI
- https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/161
- DOI
- 10.5573/JSTS.2019.19.4.378
- ISSN
- 1598-1657
- Abstract
- A 10-bit 100-MS/s pipelined SAR ADC which consists of a 5-bit coarse SAR ADC with 1-bit redundancy, a dynamic amplifier for a residue amplifier, a 6-bit fine SAR ADC, and a digital error correction is proposed. One-bit redundancy generation for a digital error correction is designed using a capacitor-based DAC used in the 5-bit coarse SAR ADC for a sub-ADC of a pipelined ADC. The input range calibration and dynamic amplifier with gain compensation circuit are proposed to improve the linearity of the pipelined SAR ADC. The proposed pipelined SAR ADC has been implemented using a 65-nm 1-poly 8-metal CMOS process with a 1.2-V supply voltage. Its active area and power consumption are 410 mu m x 425 mu m and 4.35 mW, respectively. The measured SNDR are approximately 53.47 dB for a 2.4 V-pp differential sinusoidal input with a frequency of 9.99 MHz.
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - School of Electronic Engineering > 1. Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.